Date of introduction:  1968 (Announced before December '67)
Date of withdrawal:    1971.
Total production run:  3698.

Technology:  DEC M-series logic modules, called M-series flip-chips
	as the term flip-chip was applied to the module format instead
	of to DEC's hybrid integrated circuits.  M-series modules used
	TTL chips, with a +5 volt supply, packaged on the same board
	format used with the original flip-chips, but with double-sided
	card-edge connectors (36 contacts instead of 18).  Modules were
	limited to typically 4 SSI ICs each.  The M113, a typical
	M-series module, had 10 2-input nand gates and cost $23 in 1967
	(the price fell to $18 in 1970).  Wire-wrapped backplanes used
	30-gauge wire.

	The PDP-8/I, as originally sold, supported the then-standard
	PDP-8 negibus.  4K words of core were packaged in a 1 inch thick
	module made of 5 rigidly connected 5 by 5 inch two-sided printed
	circuit boards.  Connectors and support electronics occupied an
	additional 32 backplane slots.

	Nominally, the core memory (which, curiously, used a negative
	logic interface!) was supposed to run at a 1.5 microsecond cycle
	time, but many early PDP-8/I systems were delivered running at a
	slower rate because of memory quality problems.  DEC went through
	many vendors in the search for good memory!  The memory interface
	was asynchronous, allowing the CPU to delay for slow memory.  DEC
	continued to make the classic PDP-8 until the problems with
	memory speed were solved.

Reason for introduction:  This machine was developed in response to the
	introduction of DIP component packaging of TTL integrated
	circuits.  This allowed a machine of about the same performance
	as the original PDP-8 to fit in about half the volume and sell
	for a lower price.

Reason for withdrawal:  The PDP-8/E made slight performance improvements
	while undercutting the price of the PDP-8/I.

Compatability:  The core of the PDP-8 instruction set is present, and
	unlike the original PDP-8, IAC can be combined with rotate in a
	single microcoded Group 1 OPR instruction.  Combined RAR and RAL
	or RTR and RTL produce the logical and of the expected results
	from each of the combined shifts.

	If the extended arithmetic element is present, the SWP (exchange
	AC and MQ) instruction works, but this was not documented.

	On large memory configurations, memory fetches from a nonexistant
	memory field take about 30 microseconds (waiting for a bus
	timeout) and then they return either 0000 or 7777 depending on
	the memory configuration and the field that was addressed.

	A front panel bug prevented continue after load-address without
	first clearing the machine.

Standard configuration:  CPU with 4K of memory, plus 110 baud current
	loop teletype interface.  Pedestal, table-top and rack-mount
	versions were made.  The pedestal mounted version was futuristic
	looking; the table-top version split the pedistal, with the CPU
        on the table and the power supply (the base of the pedistal) on
	the floor beside the table.  The standard rack-mounted version
	had the power supply bolted to the right side of the rack while
	the CPU, mounted on slides, slid out of the left side of the rack.

Expandability: 4K of memory could be added internally, and additional
	memory could be added externally using a rack-mounted MM8I memory
	expansion module for each 4K or 8K addition over 8K.

	The backplane of the PDP-8/I was prewired to hold a Calcomp
	plotter interface, with the adjacent backplane slot reserved
	for the cable connection to the plotter.  There may be other
	built-in options.

	Initially, the CPU was sold with bus drivers for the PDP-8
	negibus, allowing this machine to support all older DEC
	peripherals, but later machines were sold with posibus interfaces,
	and many older machines were converted in the field.

	A posibus to negibus converter, the DW08A, allowed use of all
	older PDP-8 peripherals, with small modifications.  The change
	from negibus to posibus during the period of PDP-8/I production
	leads to confusion because surviving CPUs and peripherals may
	have any of three I/O bus configurations: Negibus, early posibus,
	or final posibus.  The early posibus used the same connectors
	and cables as the negibus, with only 9 conductors per connector,
	while the final posibus used both sides of the connector paddles
	for 18 bus lines per connector.  Y-shaped cables for converting
	from one physical bus layout to the other were available.  To
	add to this confusion, some negibus PDP-8/I systems were rewired
	to use 18 conductor posibus cables with negative logic!

	Eventually, an add-on box was sold that allowed PDP-8/E (OMNIBUS)
	memory to be added to a PDP-8/I.  Additionally, Fabritek sold a
	24K memory box for the 8/I and PDP-12.

Survival:  Many PDP-8/I systems are in operating condition, some still
	performing in their original applications!