The PDP-8 word size is 12 bits, and the basic memory is 4K words.  The
minimal CPU contained the following registers:

	PC - the program counter, 12 bits.
	AC - the accumulator, 12 bits.
	L  - the link, 1 bit, commonly prefixed to AC as <L,AC>.

It is worth noting that many operations such as procedure linkage and
indexing, which are usually thought of as involving registers, are done
with memory on the PDP-8 family.

Instruction words are organized as follows:
	 _ _ _ _ _ _ _ _ _ _ _ _
	|_|_|_|_|_|_|_|_|_|_|_|_|
	|     | | |             |
	|  op |i|z|    addr     |

	op   - the opcode.
	i    - the indirect bit (0 = direct, 1 = indirect).
	z    - the page bit (0 = page zero, 1 = current page).
	addr - the word in page.

The top 5 bits of the 12 bit program counter give the current page, and
memory addressing is also complicated by the fact that absolute memory
locations 8 through 15 are incremented prior to use when used as indirect
addresses.  These locations are called auto-index registers (despite the
fact that they are in memory); they allow the formulation of very tightly
coded array operations.

The basic instructions are:

	000 - AND - and operand with AC.
	001 - TAD - add operand to <L,AC> (a 13 bit value).
	010 - ISZ - increment operand and skip if result is zero.
	011 - DCA - deposit AC in memory and clear AC.
	100 - JMS - jump to subroutine.
	101 - JMP - jump.
	110 - IOT - input/output transfer.
	111 - OPR - microcoded operations.

The ISZ and other skip instructions conditionally skip the next
instruction in sequence.  The ISZ is commonly used to increment a loop
counter and skip if done, and it is also used as an general increment
instruction, either followed by a no-op or in contexts where it is known
that the result will never be zero.

The JMS instruction stores the return address in relative word zero of
the subroutine, with execution starting with relative word one.
Subroutine return is done with an indirect JMP through the return
address.  Subroutines commonly increment their return addresses to index
through inline parameter lists or to perform conditional skips over
instructions following the call.

The IOT instruction has the following form:
	 _ _ _ _ _ _ _ _ _ _ _ _
	|1|1|0|_|_|_|_|_|_|_|_|_|
	|     |           |     |
	|     |   device  | op  |

The IOT instruction specifies one of up to 8 operations on one of 64
devices.  Typically (but not universally), each bit of the op field
evokes an operation, and these can be microcoded in right to left
order.  Prior to the PDP-8/E, there were severe restrictions on the
interpretation of the op field that resulted from the fact that the
operation was delivered as a sequence of IOP pulses, each on a separate
line of the I/O bus.  Each line was typically used to evoke a different
device function, so essentially, the operation 000 was always a no-op
because it evoked no functions, and the code 111 evoked all three
functions in series.

As an example of the use of IOT instructions, consider the console
terminal interface.  On early PDP-8 systems, this was always assumed to
be an ASR 33 teletype, complete with low-speed paper tape reader and
punch.  It was addressed as devices 03 (the keyboard/reader) and 04
(the teleprinter/punch):
	 _ _ _ _ _ _ _ _ _ _ _ _
	|1|1|0|_|_|_|_|_|_|_|_|_|
	      |0 0 0 0 1 1|0 0 1  - KSF - keyboard skip if flag
	      |0 0 0 0 1 1|0 1 0  - KCC - keyboard clear flag
	      |0 0 0 0 1 1|1 0 0  - KRS - keyboard read static

The keyboard flag is set by the arrival of a character.  The KCC
instruction clears both the flag and the accumulator.  KRS ors the 8 bit
input data with the low order 8 bits of AC.  The commonly used KRB
instruction is the or of KCC and KRS.  To await one byte of input, use
KSF to poll the flag, then read the byte with KRB.
	 _ _ _ _ _ _ _ _ _ _ _ _
	|1|1|0|_|_|_|_|_|_|_|_|_|
	      |0 0 0 1 0 0|0 0 1  - TSF - teleprinter skip if flag
	      |0 0 0 1 0 0|0 1 0  - TCF - teleprinter clear flag
	      |0 0 0 1 0 0|1 0 0  - TPC - teleprinter print static

The teleprinter flag is set by the completion of the TPC operation (as
a result, on startup, many applications output a null in order to get
things going).  TCF clears the flag, and TPC outputs the low order 8
bits of the accumulator.  The commonly used TLS instruction is the or
of TCF and TPC.  To output a character, first use TSF to poll the flag,
then write the character with TLS.

IOT instructions may be used to initiate data break transfers from block
devices such as disk or tape.  The term "data break" was, for years,
DEC's preferred term for cycle-stealing direct-memory-access data
transfers.

Some CPU functions are accessed only by IOT instructions.  For example,
interrupt enable and disable are IOT instructions:
	 _ _ _ _ _ _ _ _ _ _ _ _
	|1|1|0|_|_|_|_|_|_|_|_|_|
	      |0 0 0 0 0 0|0 0 1  - ION - interrupts turn on
	      |0 0 0 0 0 0|0 1 0  - IOF - interrupts turn off

An interrupt is requested when any device raised its flag.  The console
master clear switch resets all flags and disables interrupts.  In
effect, an interrupt is a JMS instruction to location zero, with the
side effect of disabling interrupts.  The interrupt service routine
is expected to test the device flags and perform the operations needed
to reset them, and then return using ION immediately before the indirect
return JMP.  The effect of ION is delayed so that interrupts are not
enabled until after the JMP.

The instructions controlling the optional memory management unit are
also IOT instructions.  This unit allows the program to address up to
32K of main memory by adding a 3 bit extension to the memory address.
Two extensions are available, one for instruction fetch and direct
addressing, the other for indirect addressing.

A wide variety of operations are available through the OPR microcoded
instructions:
         _ _ _ _ _ _ _ _ _ _ _ _
Group 1 |1|1|1|0|_|_|_|_|_|_|_|_|
	         1                - CLA - clear AC
	           1              - CLL - clear the L bit
                     1            - CMA - ones complement AC
                       1          - CML - complement L bit
                               1  - IAC - increment <L,AC>
                         1 0 0    - RAR - rotate <L,AC> right
                         0 1 0    - RAL - rotate <L,AC> left
	                 1 0 1    - RTR - rotate <L,AC> right twice
	                 0 1 1    - RTL - rotate <L,AC> left twice

In general, the above operations can be combined by oring the bit
patterns for the desired operations into a single instruction.  If none
of the bits are set, the result is the NOP instruction.  When these
operations are combined, they operate top to bottom in the order shown
above.  The exception to this is that IAC cannot be combined with the
rotate operations on some models, and attempts to combine rotate
operations have different effects from one model to another (for example,
on the PDP-8/E, the rotate code 001 means swap 6 bit bytes in the
accumulator, while previous models took this to mean something like
"shift neither left nor right 2 bits").
         _ _ _ _ _ _ _ _ _ _ _ _
Group 2 |1|1|1|1|_|_|_|_|_|_|_|0|
                   1     0        - SMA - skip on AC < 0  \
                     1   0        - SZA - skip on AC = 0   > or group
                       1 0        - SNL - skip on L /= 0  /
                   0 0 0 1        - SKP - skip unconditionally
                   1     1        - SPA - skip on AC >= 0 \
                     1   1        - SNA - skip on AC /= 0  > and group
                       1 1        - SZL - skip on L = 0   /
                 1                - CLA - clear AC
                           1      - OSR - or switches with AC
                             1    - HLT - halt

The above operations may be combined by oring them together, except that
there are two distinct incompatible groups of skip instructions.  When
combined, SMA, SZA and SNL, skip if one or the other of the indicated
conditions are true (logical or), while SPA, SNA and SZL skip if all of
the indicated conditions are true (logical and).  When combined, these
operate top to bottom in the order shown; thus, the accumulator may be
tested and then cleared.  Setting the halt bit in a skip instruction is
a crude but useful way to set a breakpoint for front-panel debugging.
If none of the bits are set, the result is an alternative form of no-op.

A third group of operate microinstructions (with a 1 in the least
significant bit) deals with the optional extended arithmetic element to
allow such things as hardware multiply and divide, 24 bit shift
operations, and normalize.  These operations involve an additional data
register, MQ or multiplier quotient, and a small step count register.
On the PDP-8/E and successors, MQ and the instructions for loading and
storing it were always present, even when the EAE was absent, and the
EAE was extended to provide a useful variety of 24 bit arithmetic
operations.