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Question by Mahen
Submitted on 5/7/2005
Related FAQ: N/A
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Hi
I am new to this group & first time posting a question.
It is very urgent pl respond immediately .

I am using Actel’s Libero tool which has synplify for synthesis .

I am using 8 clock signals in my design, which are used to drive many inputs.
According to synplify reference manual , tool will includes the global buffers for signals which have high fanout.

Still I am getting warnings in place & rote (designer used for place & rote which takes input an EDIF netlist generated by synplify)  for many signals as

Warning: Non-global resource 'wr_latch' is being used to drive multiple clock pins. Clock pins should be driven by global resources if available.

Pl let me know the how to remove this warnings asap.



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