Can anyone provide me verilog code for div by 3 clock with...

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Question by verilog_newbee
Submitted on 1/3/2004
Related FAQ: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
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Can anyone provide me verilog code for div by 3 clock with 50% duty cycle and which can be synthesized.

Answer by Tom
Submitted on 5/8/2004
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If the frequency of the clock if known(before dividing)--lets say that you are using a Xilinx FPGA that has an internal clock of 50MHz: to divide that by 3 (16.67 MHz), all you would need to do is write a counter that would count from 0 to ceiling(50/16.67). When the counter has reached its limit(The MSB is 1)--this is the clock that is divide by three, reset the counter and place the items that you want to be executed inside: count = count+1; if (count==some_number) begin actions here; end

Answer by krs_1980
Submitted on 7/20/2005
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Hi, Assume that you have a reset,with this reset(initialize 2 bit counter to 2'b01 with the reset) run a 2 bit counter repetitively from 1 to 3 (i.e 1, 2, 3, 1, 2 , 3 ....) with the rising edge of clock. Then take the MSB of this counter and pass it through a D-flipflop with the falling edge of clock as its active edge.And name this signal as "MSB_1D". Then pass the signals "MSB" of 2-bit counter and "MSB_1D" through an "AND" gate. The output of this "AND" gate will be your divide by 3 clock with 50% duty cycle.

Answer by shiv
Submitted on 9/26/2006
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Write a mod 3 counter and make output high whenever cnt = 3. always @(posedge clk or negedge rst_n) begin if (!rst_n) cnt <= 2'b00; else if (cnt == 2'b10) begin cnt <= 2'b00; div3 <= 1'b1; end else begin cnt <= cnt + 1'b1; div3 <= 1'b0; end end But this div3 didn't 50% duty cycle.. to get 50% duty cycle, we have to negedge always @(negedge clk or negedge rst_n) begin if (!rst_n) div3_d <= 1'b0; else div3_d <= div3; end So 50% duty cycle clock can be generated by oring these 2 signals assign div3_50_duty = div3 \| div3_d;

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