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comp.lsi.cad Frequently Asked Questions With Answers (Part 4/4) [LONG]

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Archive-name: lsi-cad-faq/part4
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Url: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html

See reader questions & answers on this topic! - Help others by sharing your knowledge
  Unix: X11;  PC: MS-Windows (math coprocessor required).

          Contact information
          -------------------
          Martti Valtonen                         Heikki Rekonen
          Helsinki University of Technology       Nokia Research Center
          Circuit Theory Laboratory               Hardware Design Technology
          Otakaari 5A, SF-02150 Espoo, FINLAND    P.O.Box 156, SF-02101 Espoo,
                                                  FINLAND
          Fax:  358-0-460224                      Tel:  358-0-43761
          e-mail:martti@aplac.hut.fi              Fax:  358-0-455 2557

          A        WWW        server        is         available         at
          <URL:http://picea.hut.fi/aplac/main.html>,  and  an  experimental
          hypertext              tutorial               is               at
          <URL:http://picea.hut.fi/aplac/tutorial/main.html>

  Free (university version) binaries for HP9000/700, Sun4, and PC machines
  are available via FTP from ftp://nic.funet.fi/pub/cae/aplac . Help files,
  PS manuals, and collections of APLAC examples are in the same directory.

53: SLS, a switch-level simulator

  (from comp.lsi.cad)

  DELFT UNIVERSITY OFFERS UNIQUE SWITCH-LEVEL SIMULATOR

  SLS is a switch-level simulator that can be used to simulate the logic
  and timing behavior of large digital circuits that are described at the
  (mixed) MOS transistor, gate and functional level.  It has fast and accu-
  rate algorithms to predict the timing behavior of MOS circuits containing
  > 100,000 transistors.  MOS transistor-level circuit descriptions are
  easily mixed with gate-level and functional-level circuit descriptions,
  where the behavior of the latter are described in the C programming
  language.  There is an X-window based user-interface to graphically edit
  the input signals and to inspect the simulation output signals. The same
  interface is used to alternatively simulate the circuit with the well-
  known circuit simulator SPICE.  SLS has already been used by many people
  at many different sites, and numerous chips have been designed with it.
  SLS is now made available world-wide to serve as a useful design and
  verification tool to the international design community.  Apart from
  being used as a stand-alone tool, SLS can also be used as a part of the
  popular design system for Sea-Of-Gates circuits OCEAN, or it can be con-
  nected to the advanced Nelsis CAD framework.

  The SLS simulator has three different simulation levels:

  1. Purely logic simulation based on abstract transistor strengths:
     This level more or less behaves similar to the original switch-level
     model as proposed by R.E. Bryant.  It computes logic states by
     only considering node states and transistor types.

  2. Logic simulation based on exact transistor dimensions and node
     capacitances: This level uses resistance division and capacitance
     division algorithms to compute logic states. It finds correct logic
     states in much more situations than conventional switch-level
     simulators, e.g. when a resistance division occurs between a saturated
     transistor and a non-saturated transistor.

  3. Logic and timing simulation based on transistor and node parameters:
     RC time constant evaluations are used to approximate real voltages by
     PIECEWISE-LINEAR VOLTAGE WAVEFORMS. This not only provides delay times
     for the circuit, but is also delivers an accurate representation for
     transient effects like spikes and races.

  Apart from electrical network elements like MOS transistors, resistors
  and capacitors, an SLS network may contain (i) gate primitives like
  inverters, nands, nors, etc. and (ii) user-defined function blocks like
  roms, shiftregisters, multipliers.  The behavior of function blocks is
  described by the user in the C programming language: it is specified by
  the user how the values of the output terminals and the state variables
  are computed from the values of the input terminals and the state vari-
  ables.

  For more information about SLS, see,

    "Switch-level timing simulation," P.M. Dewilde, A.J. van Genderen,
    A.C. de Graaf, Proc. ICCAD 85 Conf., Santa Clara, Nov. 1985,
    pp. 182-184

    "SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage
    waveforms," A.J. van Genderen, Proc. VLSI 89 Conf., Munich, Aug. 1989,
    pp. 79-88.

    "SLS: Switch-Level Simulator User's Manual," A.C. de Graaf, A.J. van
    Genderen, Delft University of Technology (available for ftp at the
    address below).

  Availability:

  SLS is written in C and runs under UNIX and X-windows.  It runs, among
  other things, on Sun SPARC stations, HP 9000 series 700/800 machines, and
  PCs running Linux.  The program is available for free under the terms of
  the GNU General Public License.  It can be retrieved via anonymous ftp
  from ftp://dutentb.et.tudelft.nl/pub/sls .

  It is also possible to obtain SLS as a part of the OCEAN system for the
  design of Sea-Of-Gates circuits.  This system can be obtained from on
  ftp://donau.et.tudelft.nl/pub/ocean .  The OCEAN system among other
  things contains a layout-to-circuit extractor that can extract large lay-
  outs and that stores the result directly in the database that is read by
  SLS.  Furthermore, SLS is available as a tool in the Nelsis CAD framework
  from the directory pub/nelsis on dutente.et.tudelft.nl.  The latest ver-
  sion of SLS can always be found on dutentb.et.tudelft.nl .

  For questions, remarks and bug reports, contact

            Arjan van Genderen
            Delft University of Technology
            Department of Electrical Engineering
            Mekelweg 4                          phone: 31-15-786258
            2628 CD  Delft                      fax: 31-15-623271
            The Netherlands                     email: arjan@dutentb.et.tudelft.nl

  54: OCEAN, a sea-of-gates design system

  (from Patrick Groeneveld <ocean@donau.et.tudelft.nl>)

          About OCEAN: the sea-of-gates design system
          -------------------------------------------

  OCEAN is a comprehensive chip design package which was developed at Delft
  University of Technology, the Netherlands. It includes a full set of
  powerful tools for the synthesis and verification of semi-custom sea-of-
  gates and gate-array chips.  OCEAN covers the back-end of the design tra-
  jectory: from circuit level, down to layout and a working chip. In a nut-
  shell, OCEAN has the following features:

          + Available for free, including all source code.
          + Short learning curve making it suitable for student design courses.
          + Hierarchical (full-custom-like) layout style on sea-of-gates.
          + Powerful tools for placement, routing, simulation and extraction.
          + Any combination of automatic and interactive manual layout.
          + OCEAN can handle even the largest designs.
          + Running on popular HP, Sun and 386/486 PC machines, easy
            installation.
          + Includes three sea-of-gates images with libraries and a
            200,000 transistor sea-of-gates chip.
          + Can be easily adapted to arbitrary images with any number of layers.
          + Interface programs for other tools and systems (SIS, cadence, etc.)
          + Robust and 'combat-proven', used by hundreds of people.

   How to retrieve OCEAN and additional documentation?
   ---------------------------------------------------

  The entire OCEAN system is available for free via anonymous ftp, gopher
  or on tape. A powerful installation script is included, so you can get
  started very quickly without hacking up the code. You can retrieve OCEAN
  and additional documentation via:

          anonymous ftp: <URL:ftp:donau.et.tudelft.nl:pub/ocean>
          gopher:        olt.et.tudelft.nl (port 70) or use the path
                         World --> Europe --> Netherlands -->
                         Delft University of Technology Electronic Engineering
                         --> Research activities -->
                         The OCEAN sea-of-gates Design System

  We advise to retrieve first the documents with the user manual. (The file
  'ocean_docs.tar.gz').  If you have any questions, remarks or problems,
  just contact us:

          Patrick Groeneveld or Paul Stravers
          Electronic Engineering Group, Electrical Engineering Faculty
          Delft University of Technology
          Mekelweg 4, 2628 CD   Delft  The Netherlands
          Phone: +31-15786240  Fax: +31-15786190
          Email: ocean@donau.et.tudelft.nl

55: ALLIANCE, a CAD package and simulator for teaching digital VLSI design

  --- (from Frederic PETROT <fred@cao-vlsi.ibp.fr>)

          ******************************************************
          *  ANNOUNCEMENT OF ALLIANCE RELEASE 3.0  May 10th 95 *
          ******************************************************

          The release 3.0 of the public domain  ALLIANCE VLSI/CAD system is
          now available at:

          ftp.ibp.fr      [132.227.60.2]        in /ibp/softs/masi/alliance

  CONTENT

  ALLIANCE is a complete set of CAD tools  and  portable  libraries for
  research and education in digital VLSI design.  The ALLIANCE CAD  system
  has been developed at the MASI laboratory (Universite Pierre et Marie
  Curie, Paris France). It includes a VHDL compiler and simulator, logic
  synthesis tools, automatic place and  route, DRC,  extractor,  functional
  abstraction  and formal proof tools etc...  All the ALLIANCE cell
  libraries  use  a  symbolic  layout approach in  order  to provide pro-
  cess independence: Cmos process from 1.6 micron to 0.8 micron have been
  successfully targetted.

  Several new  tools have been introduced into release 3.0, (...and several
  bugs have been fixed)

  1) FPGA synthesis
     The logic synthesis tool ALLIGATOR is dedicated to fast prototyp-
     ing  on  XILINX  FPGAs.  The input description uses the same VHDL
     subset as the ASIMUT VHDL simulator.

  2) Floor-plan router
     The high performance floor-plan router CHEOPS, developped by BULL
     is  part of this release. This toll uses the same symbolic layout
     approach as all the ALLIANCE portable libraries. It as been  used
     for  multi-millions  transistors  circuits.  Only the binary code
     for SPARC is available.

  3) Timing analysis
     The ALLIANCE design-flow separates functionnal verification  (us-
     ing  zero  delay  VHDL  models) and the timing verification.  The
     timing analyser TAS takes an extracted, transistor level net-list
     (ALLIANCE  or  SPICE  format) as input, and provides all relevant
     timing information.

  INSTALLATION

  ALLIANCE is totally free, under the terms of the GNU General Pub- lic
  License.  It includes C source files and on-line English do- cumentation
  (UNIX man)

  1) A hierarchical makefile allows each ALLIANCE tool to  be  com-
     piled and  installed separately.  The disk  space  required to
     compile  and  install  the full  ALLIANCE package is about 150
     megs.

  2) The release 3.0 has been successfully compiled with K&R cc and
     GNU gcc compilers. The full alliance package can  now  run  on
     SPARC, LINUX and DEC architectures.

  TUTORIALS

  The release ALLIANCE 3.0 contains six separate tutorials:

  1/ ADDACCU
     The  design  of a  very simple chip (adder/accumulator) to get
     started with the ALLIANCE tools (about 500 transistors).

  2/ AMD2901
     The design of the 4 bits AMD2901 processor, from the VHDL spe-
     cification  to the  GDSII  layout, using the ALLIANCE portable
     standard cell library (about 3000 transistors).

  3/ DLX
     The  design of the 32 bits DLX microprocessor (HENNESSY & PAT-
     TERSON) from the VHDL specification to the GDSII layout, using
     the  ALLIANCE  data-path  compiler  and  logic synthesis tools
     (about 30000 transistors).

  4/ FPGA
     The synthesis of a simple circuit on Xilinx  FPGA (Field Prog-
     rammable Gate Array). The produced cirucit uses 20 CLBs.

  5/ Synthesis Tools
     Different  levels of synthesis  and optimization (Finite State
     Machine synthesis, logic synthesis, logic and net-list optimi-
     zations) are covered by this tutorial.

  6/ Data Path
     Building simple data paths  using the data path compiler FPGEN
     and the data path router DPR.

56: ceBox EDIF Viewer and Schematic Generator

  <from comp.archives>

  A free demo version of the ceBox EDIF Viewer is now available from the
  the following site:

          ftp://www.concept.de/

  you find the following files:

          README                             3k

          nlview-2.5-sun.tar.gz            856k   for SPARC SunOS4+5
          nlview-2.5-hp.tar.gz            1168k   for HP-PA
          nlview-2.5-win32.zip             536k   for Windows95+WindowsNT
          doc-2.5-sun.tar.gz                88k   Documentation
          doc-2.5-hp.tar.gz                 88k   Documentation
          doc-2.5-win32.zip                 89k   Documentation

  The  *ceBox EDIF Viewer*  displays schematic pages and symbols of any
  EDIF 200 (level 0) file. It is an easy-to-use tool to analyse EDIF
  schematic and EDIF netlist files.

  The  *ceBox EDIF Kit*  is a programming library to bundle C++ user func-
  tions to the Viewer and to build standalone EDIF processors.  The Kit's
  in-core data base allows to access/modify all EDIF data.

  A free demo version of nlview (schematic generation and viewing tool) for
  SPARCstation is available via anonymous ftp from:

          ftp://ftp.Germany.EU.net/shop/concept-engineering/
          [192.76.144.75]

  The tool reads EDIF 200 netlist files or structural Verilog files,
  creates schematics and displays them on screen. Some extra functions are:

          +      cross-probing between schematic and ASCII file

          +      searching objects by name (using wild-cards)

          +      highlighting critical pathes (infos from separate file)

          +      writing EDIF 200 schematic and PostScript files

  For more information, please contact:

          Concept Engineering
          Burkheimer Str. 10
          D-79111 Freiburg, Germany

          Tel: ..49-761-473099
          Fax: ..49-761-441063
          email: info@concept.de

57: Analog CMOS VLSI Design Educational Resource Kit

  (from MUG)

  UMass Dartmouth is pleased to announce the release of Version 1 of the
  Analog CMOS VLSI Design Educational Resource Kit.  Version 1 of the
  Resource Kit may be obtained via anonymous ftp at the site

          micron.ece.umassd.edu

  The release includes the following files and information:

  The CIF file for a 2 micron Mosis Tinychip using p-well technology; and
  manuals containing five tutorials based on the chip set.

  These circuits were used in an undergraduate course on analog VLSI design
  during the spring semester at the University of Massachusetts Dartmouth.
  They are also being currently used in a graduate level course in analog
  VLSI design.  The students in the undergraduate course had a single
  introductory digital VLSI design course as background, and were familiar
  with MAGIC, SPICE and CAzM, a SPICE-like circuit simulator.

  If you have any comments, corrections or suggestions regarding the
  release, or ideas for other circuits that you have found useful in your
  classes and that could be incorporated in later releases, please feel
  free to contact me.  Good luck!

          Robert H. Caverly, Ph.D.
          ECE Department
          University of Massachusetts Dartmouth
          N. Dartmouth, MA  02747
          caverly@micron.ece.umassd.edu
          (508) 999-8474

58: TDX Fault Simulation and Test Generation Software

  (from Dan Holt <dan@attest.com>)

  TDX Fault Simulation and Test Generation Software

  Free demo/student copies of Attest Software's fault simulation, Iddq,
  DFT, and automatic test pattern generation tools are available by
  anonymous ftp.

  This software is fully functional on any circuit with less than 200
  gate-level primitives. It is also fully functional on the GL85 micropro-
  cessor circuit (about 3000 primitives) which is included with the suite
  of tools. General-use licenses can be provided free to accredited univer-
  sities for non-commercial, educational purposes.

  The software is built around a high-performance concurrent fault simula-
  tor that is accurate on a wide-range of state and timing sensitive cir-
  cuits. It supports synchronous and asynchronous designs containing logic
  gates, MOS transistors, tri-state buffers, flip-flops, single/multi-port
  RAMs, complex bus resolution functions, and Verilog User Defined Primi-
  tives (UDPs).  The software also supports the detailed pin timing and
  strobing features found on "tester-per-pin" automatic test equipment. The
  software supports Verilog and VHDL netlists.

  The GL85 microprocessor, which is a clone of the once-popular 8085
  microprocessor, is a fully functional model for which three views are
  provided: behavioral, RTL, and gate level.  Using this clone, a tutorial
  shows the user how to achieve improved controllability and/or observabil-
  ity for his or her circuit, resulting in improved fault coverage, some-
  times with very little additional time or effort expended in the design
  cycle. The tutorial was written by Dr. Alex Miczo.

  The software is available by ftp at:

          <URL:ftp://ftp.attest.com/pub/>

  The README contains installation instructions, and identifies the loca-
  tion of the GL85 models and the postscript tutorial. The web page is:

          <URL:http://www.attest.com/>

  For more information, please contact:

          Attest Software Inc.
          47100 Bayside Parkway
          Fremont CA 94538-9942  USA

          (510) 623-4253  voice
          (510) 623-4550  fax

          info@attest.com

59: Nascent Technologies CDROM - magic and spice releases for Linux

  The Linux from Nascent CDROM, Version 1.0, is only $39.95 plus shipping
  and handling, and comes with an 30-day unconditional money-back guaran-
  tee.  If you aren't completely satisfied, return the package with your
  receipt within 30 days and the purchase price, excluding shipping and
  handling, will be refunded to you.

  In addition, Nascent offers the Linux from Nascent Plus package for only
  $89.95, which includeds six months of email support and a 30% discount
  off a future release of the CDROM with your CDROM purchase.

          Nascent Technology
          811 Haverhill Drive
          Sunnyvale CA 94087 USA
          Tel: (408) 737-9500
          Fax: (408) 241-9390
          Email: nascent@netcom.com

  Linux is a freely distributable Unix(R) compatible operating system for
  the IBM(R) 386/486 PC and compatibles written by Linus Torvalds from the
  University of Helsinki, Finland.  It was developed by a unique world-wide
  collaboration of programmers over the internet, and is covered by the GNU
  General Public License.  Linux is a modern, high performance network
  operating system, much like ones used for years on engineering and pro-
  fessional workstations.

  The Linux from Nascent CDROM is an entirely new distribution of the Linux
  operating system, and includes over 400 mbytes of source code, binaries,
  and documentation for Linux and applications.  The Linux from Nascent
  distribution features:

          * 52 page User Guide
          * automated root, swap, and package installation from CDROM
          * simple user account and network administration scripts
          * Linux 0.99.14 plus net-2 networking
          * extensive online documentation and manuals
          * network printer support
          * X Window System(TM)
          * OpenLook(TM) 3d window manager
          * SCSI disk and tape support
          * TeX(TM) and ghostscript word processor and viewer
          * Ingres database management
          * GNU C compiler and utilities
          * GNU emacs, vi clone text editors
          * sound and graphics support
          * Over 100 high resolution images translated from Kodak PhotoCD(TM)
          * magic and spice electronic design tools
          * GNU Chess, Shogi, pooltable, xpilot, flight simulator, ...

60: Time Crafter 1.0, a timing diagram documentation tool

  (from Rick Burgett <burgett@csips1.nrlssc.navy.mil>)

  I have uploaded to the SimTel Software Repository (available by anonymous
  ftp from the primary mirror site
  ftp://OAK.Oakland.Edu/pub/msdos/electric/ and its mirrors):
  timecrft.zip    WIN3: Electronic ckt timing diagram generator

  Time Crafter Version 1.0 is a timing diagram documentation tool.  A tim-
  ing diagram is used by electrical engineers and technicians to document
  the way a circuit or system operates or should operate.  This type of
  documentation is crucial to good design and debugging but up to now one
  could only use paper and pencil (with a good eraser) or an expensive CAD
  package costing $1000 or more to produce these diagrams on a PC.  Time
  Crafter has features that make it easy to document and update a circuit
  design of any complexity.

  Time Crafter is Microsoft Windows based to provide a simple yet powerful
  user interface which is device independent.

  Special requirements: Windows 3.x

  61: ACS, a general purpose mixed analog and digital circuit simulator

  (from comp.lsi.cad)

  A new version of ACS (Al's Circuit Simulator) has been posted to
  alt.sources.  It is also available by ftp from ftp://cs.rit.edu/pub/acs
  or ftp://ee.rochester.edu/pub/ .   If you don't have net access you
  can get it by dial-up from (USA) 716-272-1645.

  ACS is a general purpose mixed analog and digital circuit simulator.  It
  performs nonlinear dc and transient analyses, fourier analysis, and ac
  analysis linearized at an operating point.  At this point the analog is
  stronger than the digital.  (In fact, the digital part is rather weak.)
  It is fully interactive and command driven.  It can also be run in batch
  mode or as a server.  The output is produced as it simulates.  Spice com-
  patible models for the MOSFET (level 1 and 2) and diode are included in
  this release.

  This version (0.13) includes several improvements including real Fourier
  analysis and better time step control based on truncation error.  There
  are other minor improvements.

  Since it is fully interactive, it is possible to make changes and re-
  simulate quickly.  The interactive design makes it well suited to the
  typical iterative design process used it optimizing a circuit design.  It
  is also well suited to undergraduate teaching where Spice in batch mode
  can be quite intimidating.  This version, while still officially in beta
  test, should be stable enough for basic undergraduate teaching and
  courses in MOS design, but not for bipolar design.

  In batch mode it is mostly Spice compatible, so it is often possible to
  use the same file for both ACS and Spice.

  The analog simulation is based on traditional nodal analysis with itera-
  tion by Newton's method and LU decomposition.  An event queue and incre-
  mental matrix update speed up the solution for large circuits.

  It also has digital devices for true mixed mode simulation.  The digital
  devices may be implemented as either analog subcircuits or as true digi-
  tal models.  The simulator will automatically determine which to use.
  Networks of digital devices are simulated as digital, with no conversions
  to analog between gates.  This results in digital circuits being simu-
  lated faster than on a typical analog simulator, even with behavioral
  models.  The digital mode is experimental and needs work.  There will be
  substantial improvements in future releases.

  The source and documentation can be obtained by anonymous ftp from
  ftp://ee.rochester.edu/pub/ or ftp://cs.rit.edu/pub/acs .  It can also
  be obtained by dial-up (USA) 716-272-1645 in /pub/acs.  It may be distri-
  buted under the terms of the GNU general public license.  The dial-up
  also has some test circuits, pre-compiled executables for Next, Sun4,
  MSDOS and possibly others, and documentation in dvi and postscript.

62: LOG/iC, a logic synthesis package for PLDs

  (from Ralph Remme <RR@ns.isdata.de>)

          LOG/iC EVAL
          - - ISDATA GmbH Karlsruhe, Germany / ISDATA Inc. Oakland CA
          - - FSM and logic synthesis for programmable logic devices
          - - Several output formats: JEDEC, POF, HEX, EDIF, XNF, Open-PLA,
              PALASM, ...
          - - PLD data base as an electronic reference
          - - PC Windows
          - - free version of LOG/iC PLUS for educational and research use only
          - - anonymous ftp: ftp://gate.fzi.de/pub/ (141.21.4.3)
          - - email: isdata@isdata.de

          ISDATA GmbH                     ISDATA Inc.
          Daimlerstrasse 51               P.O. Box 19278
          D-76185 KARLSRUHE               Oakland, CA 94619
          GERMANY                         U.S.A.
          Phone:(+49) 721 75 10 87        Phone: (++1) 510 5318553
          FAX:   (+49) 721 75 26 34       Fax:   (++1) 510 5318417
          Mr. Peter Bauer                 Mr. Paul Hoy

  An evaluation copy of LOG/iC2 is available:

          LOG/iC2 EVAL
          - ISDATA, Germany
          - Logic synthesis and simulation for PLDs 16V8, 20V8 and 22V10 from all
            manufacturers
          - Input: Hierarchical entry supported by the graphical hierarchy
            editor, high level description language, 74xx library,
            macrogenerator
          - Output: Programming file (JEDEC)
          - includes the PLD data base, an electronic reference manual
          - Functional simulator
          - PC version for Win 3.1 and Win 95
          - CD can be ordered free of charge at ISDATA via email: isdata@isdata.de

          The full version of LOG/iC2 supports CPLDs from nearly all vendors,
          FPGAs from Xilinx and Actel, and all Simple PLDs.
          It offers timing simulation and as an option VHDL entry.

63: SIMLAB, a circuit simulation environment

  (from Bardo Muller <bardo@ief-paris-sud.fr>)

  Simlab is a circuit simulation environment consisting of a flexible,
  user-friendly front-end operating in conjunction with a sophisticated and
  versatile simulation engine.  The program is written in C and is specifi-
  cally designed to be used as an educational tool and as a research plat-
  form. Simlab can be operated in either batch or interactive mode. An
  optimized version for the Connection Machine (cmvsim) is available.

  The user is allowed to separately specify algorithms for the various
  aspects of the simulation. These include:

          Simulation environment (e.g. serial or parallel depending on
               the underlying hardware).
          ODE system solution (e.g. point)
          ODE system time integration (e.g. backward-Euler, trapezoidal,
               second-order Gear),
          Nonlinear algebraic system solution (e.g. multidimensional
               Newton's method, nonlinear relaxation),
          Linear system solution (e.g. sparse Gaussian
               elimination, Gauss-Jacobi relaxation, conjugate gradient,
                  conjugate gradient squared),

  Furthermore, simlab has a notion of simulation mode and different methods
  can be specified for different modes. At present, supported modes are DC
  for the calculation of operating points, and Transient for the calcula-
  tion of the time response of a circuit. For instance, assuming that the
  user has specified the multidimensional Newton's method for solving the
  nonlinear system of equations, the linear solver associated could be dif-
  ferent depending of what type of simulation is being performed.

  In its basic form, simlab is a powerful circuit simulator, but it is also
  designed to be easily customized for research purposes. For example, sim-
  lab forms the core of special-purpose simulation programs, such as a
  switched capacitor filter simulator and a simulator for vision circuits.
  The program code is highly modular, so that researchers can easily con-
  struct and test algorithms by inserting them into the existing simlab
  framework.

  Simlab can be obtained from ftp://rle-vlsi.mit.edu/pub/. Question
  or problems related to the installation or usage of the simlab circuit
  simulator should be addressed to simlab@rle-vlsi.mit.edu (18.62.0.214).
  Any bugs should be reported to simlab-bug@rle-vlsi.mit.edu .

64: Pcb, an X-based PC board design tool

  (from comp.windows.x.apps)

  Pcb is a handy tool for the X Window System build to design printed cir-
  cuit boards. It supports multiple layers and circuit libraries with a
  resolution of 0.001 inch.  Refer to the manual for more details.

  The new feature are:

            - user interface has been 'cleaned up'
            - number of key strokes have been reduced by menues
            - encapsulated PostScript is now supported
            - all deleted objects can be recovered
            - most of the operations can also work with 'selected' objects
            - some circuits and packages are included
            - fileselect boxes with user defined commands and preset directories
              make a flexible user interface
            - the position of element names is now changeable. Both names of an
              element are changeable
            - grid settings are either absolute (to 0,0) or relative to the
              position where it has changed
            - messages and stderr of external commands can be redirected to a
              log window

            - *** a special goodie: ***
              a functional demo layout with a Motorola 68HC11 microcontroller
              and LCD display

          ftp servers (ftp.funet.fi thanks to Matti Aarnio):
              ftp://ftp.medizin.uni-ulm.de/pub/
              ftp://ftp.funet.fi/pub/

  Please have a look at the README files before getting the preformated
  documentation.

          There is also a mailing list to share knowledge, libraries and other
          information (without too much traffic right now):
            pcb@pluto.medizin.uni-ulm.de           to reach all members
            pcb-request@pluto.medizin.uni-ulm.de   to subscribe or unsubscribe
            owner-pcb@pluto.medizin.uni-ulm.de     for problems with the list
            Thomas.Nau@medizin.uni-ulm.de          to reach the author only

65: SPICE-PAC, A Modular Spice Simulator with Enhancements

  (from Bardo Muller <bardo.muller@ief-paris-sud.fr>)

  SPICE-PAC  -  A Modular Spice Simulator with Enhancements

          Author:  W.M. Zuberek
                   Computer Science Department
                   Memorial University of Newfoundland
                   St. John's, Nfld, Canada A1C-5S7
                   tel. (709) 737-4701 or 737-8627
                   fax: (709) 737-2009

  SPICE-PAC is a mature simulation package that is, with only a few minor
  exceptions, upward compatible with the popular SPICE-2G circuit simulator
  but provides a number of extensions.

  SPICE-PAC allows the construction of interactive applications in which
  circuit simulation can be combined with different optimization methods,
  statistical analysis, symbolic simulation. High-level (behavioral) simu-
  lation is possible by user-defined functions and tables.

  The SPICE-PAC Fortran/C-source (version 94.08) can be found in the direc-
  tory ftp://ftp.cs.mun.ca/pub/sppac

66: U.C. Berkeley Low-Power Cell Library

  (from Tom Burd <burd@eecs.berkeley.edu>)

          **********************************************************************

          ======================================================================
                                U.C. Berkeley Low-Power Cell Library
          ======================================================================
            FOR CONDITIONS OF USE, PLEASE READ THE ACCOMPANYING COPYRIGHT FILE

                                          Overview:
                                          --------

  This Library is based on the Mosis (<URL:http://www.mosis.edu>) SCMOS
  Design Rules and has been implemented via the Magic 6 layout editor. The
  sdl files and oct facets provided allow the Library to be used within the
  LagerIV silicon compilation system
  (<URL:ftp://infopad.eecs.berkeley.edu/pub/lager>). Also, symbols,
  schematics, and vhdl files are provided for using the library within the
  Powerview (Trademark of Viewlogic Systems, Inc.) design environment. The
  documentation at present is available in postscript form as well as in
  FrameMaker 4 (Trademark of Frame Technology Corp.) format.  These are
  denoted as .ps and .doc files.

  This library has been used in the development of over a dozen chips here
  at U.C. Berkeley as of Dec. 1994, so it has been through several rounds
  of beta testing already.

  Since the library is naturally partioned by the type of cell, I have set
  up separate distributions for each partition:

          1. TimLagerlp          Array tiled cells. (e.g. sram, fifo, etc.)
          2. dpplp               Bitsliced cells for datapath construction.
          3. stdcell2_3lp        Standard Cell Library.
          4. pads1_0clp          1.0um pads.
          5. pads1_2clp          1.2um pads.

  Updates to the Library will be by the above partitions, such that each
  partition will have an associated version number.

  PLEASE SEND BUG-REPORTS TO burd@eecs.berkeley.edu AND PREFIX THE SUBJECT
  LINE WITH "LPLIB BUG:" FOR EASIER ACCOUNTING.

  PLEASE DO NOT DIRECT INQUIRES REGARDING HOW TO USE LAGERIV,
  POWERVIEW(TM), OR FRAMEMAKER(TM) TO MYSELF, BUT RATHER TO AN APPROPRIATE
  NEWS GROUP DISCUSSION.

          ======================================================================
                                        Installation:
                                        -------------

          1. Untar the desired partitions in an installation directory (denoted
             as LPLIB)

          2. To use with LagerIV, I have also included a "lager" file here to
             be used, that will function properly if the LPLIB environment
             variable is set.

          ======================================================================
                                        Documentation:
                                        -------------

  1. Documentation is provided within each library.  Not all docs, mainly
    the timing, may be completed.  However, all schematics and required
    parameters are given/described.  The timing characterizations that
    are done are for either MOSIS's 1.2um (HP) run (TimLagerlp, pads1_2clp,
    stdcell2_3lp), or the same process but with shifted VT's (dpplp).
    This was achieved by shifting the flat-band voltage, and used purely
    for research and not fabrication/testing purposes. The MOSIS 1.0um
    (HP's "0.8um" process, but really, lambda=0.5) parameters were used
    for the pads1_0clp library. The process parameters used is noted in
    the docs.

  2. Spice Files: I have included here the 1.2um and 1.0um spice files used
  for
    the timing.  All delays are measured 50%-50%. The BSIM models
    for used and simulated with HSPICE (Trademark Meta Software).

  3. You can also refer to my thesis for further overview of the design
    choices made, and an overview of the Library:

                  <URL:http://infopad.eecs.berkeley.edu/~burd/gpp/gpp.html#masters>
                  <URL:ftp://infopad.eecs.berkeley.edu/pub/burd/masters.ps>

67: The Substrate Resistance Extractor SUBSPACE

  (from arjan@cas.et.tudelft.nl (Arjan van Genderen))

  We have made available for anonymous FTP a program for computing sub-
  strate resistances, called SUBSPACE.  The program is based on the paper
  "Extraction of Circuit Models for Substrate Cross-Talk", by T.  Smedes,
  N.P. van der Meijs and A.J. van Genderen, Proceedings ICCAD 1995.

  The program uses as input a geometrical description of a set of contacts
  defined on top of a semi-conducting substrate.  This input is generated
  using an X-window based graphical layout editor.  The properties of the
  substrate and the parameters for the boundary-element method that is used
  to compute the substrate resistances, are specified in a parameter file.
  Effects of chip side-walls can also be included.  The output consists of
  a SPICE resistance network.

  SUBSPACE is a special version of the layout-to-circuit extractor SPACE;
  everything that SUBSPACE can, SPACE can do too.  Moreover, SPACE can
  simultaneously extract MOS and bipolar transistors, RC models and 3D
  capacitances.  Actually, the only special thing about SUBSPACE are the
  technology files and a pre-configured set of options.  The full version
  of SPACE will be released in several weeks.

  The program SUBSPACE is available in executable form, including documen-
  tation, for HP 700/800 computers and Sun Sparc stations.  It can be
  obtained via anonymous FTP from
  ftp://dutentb.et.tudelft.nl/pub/space/subspace, or via the WWW address
  specified below.

  For more information, see our WWW page:
      http://dutentb.et.tudelft.nl/research/space.html

  A tutorial is found at
      http://dutentb.et.tudelft.nl/research/subspace.html

68: XRLCAD, A C++ library for manipulating Calma (GDS) and CIF libraries

  (from Mumit Khan <khan@xraylith.wisc.edu>)

  XRLCAD -- CXrL CAD toolset

  This package contains a C++ class library to manipulate Structure (as in
  Calma/CIF) hierarchies. There is also loaders for CIF and Calma, as well
  as output drivers for these formats. A bunch of demo programs are
  included which I wrote when I was testing the library, and these programs
  turned out be quite useful tools.

  The library is still in its infancy, but it's reasonably solid; in a few
  months I'll take another look at it and probably overhaul it.

          Core directory organization: relative to $TOPDIR

              ./xrutils - standard stuff (lists, stacks, hash tables, strings)
              ./xrcad   - C++ class libraries for manipulating cell libraries
                          and the embedded structure hierarchy
              ./calma   - input/output drivers for Calma/GDS
              ./cif     - input/output drivers for CIF
              ./technology - very incomplete. Started to see if I could do what
                             Magic does with CIF layers <--> GDS layer ids.

          Demo programs: relative to $TOPDIR

              ./gdsflatten - flatten a GDS file
              ./gdsxtract - extract cell hierarchy (and specific layers)
              ./gdshier - show hierarchy
              ./gdsinfo - useful info (hierarchy, bounding box)
              ./cifflatten - flatten a CIF file (and extract specific layers)
              ./cif2gds -
              ./gds2cif -
              ./biaser - mask compensation program
              ./gdsclip - clip and extract an area of a layout

          I've successfully built a recent snapshot on the following platforms:

              sparc-sunos-4.1.3: SC2.0.1, Cfront-3.0.1, GCC-2.6.3
              sparc-sunos-5: SC2.0.1, GCC-2.6.3
              rs6000-aix-3.2: Cfront-3.0.1, GCC-2.6.3
              decstation-ultrix4.2: Cfront-3.0.1, GCC-2.6.3
                                    (and I think it worked!)

  If you use this package, please do send an email to
  <khan@xraylith.wisc.edu> so I can send you info as new enhancements and
  releases become available.

          Further information is available at

          <URL:http://www.xraylith.wisc.edu/~khan/software/xrlcad/xrlcad.html>

          %-----------------------------------------------------------------%
          Mumit Khan                        khan@xraylith.wisc.edu
          Research Staff                    Phone: +1 608 265 6075
          Center for X-ray Lithography      FAX:   +1 608 265 3811
          University of Wisconsin-Madison   http://www.xraylith.wisc.edu/~khan/
          %-----------------------------------------------------------------%

69: SAVANT, an Analyzer of VHDL Applications for Next-Generation Technology

  (From jpaul@el.wpafb.af.mil (Paul Jarusiewic Jr.))

  Extracted from <URL:http://www.ece.uc.edu~paw/quest>:

  The primary goal of SAVANT (Standard Analyzer of VHDL Applications for
  Next-Generation Technology) is to stimulate research among the VHDL com-
  munity by providing an extensible, object-oriented, well-documented
  intermediate form (IF) and a freely available analyzer to convert VHDL
  into the IF. Because the IF analyzer is released in source form, the
  additional derived classes can be inserted into the C++ class hierarchy.
  Thus, user actions can benefit fully from the fact that the IF is
  object-oriented. Consequently, no procedural interface is provided or
  needed.

70: Protel Demos for Windows

  Demos of Advanced Schematic 2.3 for Windows, Advanced PCB 2.5 for Windows
  and Protel-Easytrax (DOS Freeware) are available for download from
  www.protel.com, or ftp.protel.com.

          Advanced PCB 2.5 Disk 1 in zip form
          Advanced PCB 2.5 Disk 2 in zip form

          Advanced Schematic 2.3 Disk 1 in zip form
          Advanced Schematic 2.3 Disk 2 in zip form

          Easytrax (DOS Freeware) in zip form (this is a fully-working program)

          Autotrax Demo (DOS) in zip form

          Special Limited Edition Demo Pack

  Complete the Request form and our Sales department will send qualified
  applicants the current Limited Edition Protel Design System demo package.
  This demo pack features the special Limited Edition of Advanced PCB. The
  Limited Edition version allows you to create and save actual PCB layouts
  with up to 20 components and 200 connections. This special version also
  includes a descriptive tutorial booklet which discusses features of these
  tools. Because these tools are very easy to use, many users will be able
  to demo the products with the aid of the packages' comprehensive On-line
  Help systems.

  Note: If the desired service is not currently available, please e-mail
  your request to salesusa@protel.com or seek assistance from any of the
  available Protel contacts in your country.

71: BPECS PCB Software

  (from bstproto@connectnet.com <Steve Rabin>)

  Our new PCB Software BPECS version 1.06 features:

            Automatic path from schematics to placement to layout
            Improved autorouter
            Postscript AND Gerber output
            Camera ready art from Windows print device
            Pseudo-Teardrop pads for reduced trace breakage
            Design your own SMD packages w. mixed coordinates
            FREE 30 day evaluation - all features availible
            FREE upgrades and accessories from our web-site
            Low $295 price
            1 year limited warranty

  Visit our website to download your copy.

          ------------------------------------------------------------
              Best Proto (TM) * http://www.bestproto.com/ftpsite
            Prototyping Boards * CAD Software * Engineering Services
          Box 232440, San Diego, CA 92193-2440 * (619) 286-9000 ph/fax
          ------------------------------------------------------------

72: RF, an RF Circuit Simulation Tool

  (from Academic Technologies <academic@onthenet.com.au>)

  Analog and RF Circuit Simulation and Tool for Engineers, Radio Amateurs,
  Hobby and Students or anyone interested in linear circuit analysis and
  design.

  RF has been written as a design aid for the radio amateur, hobbyist, stu-
  dent or practicing engineer. The primary aim is as tool for radio fre-
  quency design, however the program is suitable for use in any analog
  design. Pulse response and DC circuits are encompassed in this version
  however it is not intended as a replacement or alternative to programs
  such as SPICE rather as an addition to the existing tools available. It
  is particularly aimed at high frequency small signal design using S
  parameters.

  RF runs under Windows 3.1, Windows 95 and Windows NT

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