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Archive-name: lsi-cad-faq/part1
Posting-Freqency: every 14 days Url: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html See reader questions & answers on this topic! - Help others by sharing your knowledge Welcome to comp.lsi.cad / comp.lsi: this is the biweekly posting of fre- quently asked questions with answers. Before you post a question such as "Where can I ftp spice from?", please make sure that the answer is not already here. If you spot an error, or if there is any information that you think should be included, please send us a note at clcfaq@ece.ucdavis.edu. This FAQ has recently been put on the Web in a much more readable format. Though it is still under minor construction, all of the pieces are there. Try it out at <URL:http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq- toc.html> and let us know of any problems or suggestions by mailing to clcfaq@ece.ucdavis.edu. The products and packages described here are intended for research and edu- cational use. As such, we try to limit our entries to applications which are available for free or at low cost (< $500). We also wish to limit the descriptions to at most a page (60 lines) in length. Bret Rothenberg <rothenbe@ece.ucdavis.edu> Wes Hardaker <hardaker@ece.ucdavis.edu> Mike Altarriba <altarrib@ece.ucdavis.edu> Solid State Circuits Research Laboratory Electrical Engineering and Computer Science University of California, Davis Davis, California 95616 ---------------------------------------------------------------------- $Id: comp.lsi.cad.FAQ.ms,v 1.150 1997/01/10 00:52:03 altarrib Exp $ Frequently Asked Questions with Answers ! 1: Mosis Users' Group (MUG) 2: Improved spice listing from magic. 3: Tips and tricks for magic (Version 6.3) 4: What can I use to do good plots from magic/CIF? 5: What tools are used to layout verification? 6: EDIF data exchange format. 7: What layout examples are available? 8: How can I get my lsi design fabbed and how much will it cost? 9: Mosis fabrication services. 10: Archive sites for comp.lsi.cad and comp.lsi 11: Other newsgroups and information sources that relate to comp.lsi* 12: Simulation programs tips/tricks/bugs 13: Getting the latest version of the FAQ 14: Converting from/to GDSII/CIF/Magic 15: CFI (CAD Framework Initiative Inc.) 16: What synthesis systems are there? 17: What free tools are there available, and what can they do? 18: What Berkeley Tools are available for anonymous ftp? 19: What Berkeley Tools are available through ILP? ! 20: Berkeley Spice (Current version 3f4) 21: Octtools (Current version 5.1) 22: Ptolemy (Current version 0.5) 23: Lager (Current version 4.0) 24: BLIS (Current version 2.0) 25: COSMOS and BDD 26: ITEM 27: PADS logic/PADS PCB 28: Another PCB Layout Package 29: Magic (Current version 6.5) 30: PSpice 31: Esim 32: iSPLICE3, a mixed-mode simulator for MOS/Bipolar circuits 33: Watand 34: Caltech VLSI CAD Tools 35: Switcap2 (Current version 1.1) 36: Test Software based on Abramovici text 37: Atlanta and Soprano automatic test generators 38: Olympus Synthesis System 39: OASIS logic synthesis 40: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator 41: Galaxy CAD, integrated environment for digital design for Macintosh 42: WireC graphical/procedural system for schematic information 43: LateX circuit symbols for schematic generation 44: Tanner Research Tools (Ledit and LVS) (Commercial Product) 45: SIMIC, a full-featured logic verification simulator 46: LASI CAD System, IC and device layout for IBM compatibles 47: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles 48: MagiCAD, GaAs Gate Array Design through MOSIS 49: XSPICE, extended version of Spice 50: MISIM, a model-independent circuit simulation tool 51: Nelsis Cad Framework 52: APLAC, a general purpose circuit simulation and design tool 53: SLS, a switch-level simulator 54: OCEAN, a sea-of-gates design system 55: ALLIANCE, a CAD package and simulator for teaching digital VLSI design ! 56: ceBox EDIF Viewer and Schematic Generator 57: Analog CMOS VLSI Design Educational Resource Kit 58: TDX Fault Simulation and Test Generation Software 59: Nascent Technologies CDROM - magic and spice releases for Linux 60: Time Crafter 1.0, a timing diagram documentation tool 61: ACS, a general purpose mixed analog and digital circuit simulator 62: LOG/iC, a logic synthesis package for PLDs 63: SIMLAB, a circuit simulation environment 64: Pcb, an X-based PC board design tool 65: SPICE-PAC, A Modular Spice Simulator with Enhancements 66: U.C. Berkeley Low-Power Cell Library 67: The Substrate Resistance Extractor SUBSPACE 68: XRLCAD, A C++ library for manipulating Calma (GDS) and CIF libraries 69: SAVANT, an Analyzer of VHDL Applications for Next-Generation Technology 70: Protel Demos for Windows 71: BPECS PCB Software 72: RF, an RF Circuit Simulation Tool + : new item ! : changed ? : additional information for this subject would be appreciated. 1: Mosis Users' Group (MUG) (From the Microelectronics Systems Newsletter) Microelectronic Systems News, formerly known as the MOSIS Users' Group (MUG) Newsletter, includes not only items of interest to those design- ing integrated circuits for prototyping via MOSIS but also for those designing, prototyping and producing microelec- tronic systems. Notices of new items are broadcast to about 1800 subscribers throughout the world. There is no charge for this service. To make a contribution or to be added to the email notification list, please send email to Prof. Don Bouldin at the University of Tennessee, Knoxville: dbouldin@utk.edu Microelectronic Systems News can now be accessed at: <URL:http://microsys6.engr.utk.edu/ece/msn> A variety of design files and CAD tools contributed by the members of the MOSIS Users' Group (MUG) are now available via anonymous ftp from "ftp://ftp.mosis.edu/pub/mug" (128.9.0.32). The files "readme" and "index" should be retrieved first. These files are provided "as is", but may prove very helpful to those using the MOSIS integrated circuit proto- typing service. 2: Improved spice listing from magic. Hierarchical extractions with net names: ext2spice done by Andy Burstein <burstein@eecs.berkeley.edu>: This program will do hierarchial extraction using node names. It sup- ports PS, PD, AS, and AD extraction as well. It is available for ftp from ftp://ic.eecs.berkeley.edu/pub/spice3/ . Poly and well resistance extraction: There are persistent rumors that people have this working, however, all I have seen is extracted poly resistor with each end shorted together, ie each end has the same node name/number. (This is the most annoying problem that I typically encounter daily. If ANYONE knows a fix for this, please tell us! I wrote a real quick and dirty set of scripts/programs to edit the magic file. It will break the poly contacts and relabel them. This is a real hack, but all other solu- tions require modification of the magic code itself. This procedure only works with an extractor that handles labeled nodes, i.e. ext2spice from above. --WH) Spice listing from magic with MESFETs. (from Jen-I Pi <pi@isi.edu>) We have a revised version (of sim2spice) that goes with version6. It is available from our anonymous FTP host "ftp://ftp.mosis.edu/pub/mosis/magic/" (128.9.0.32). Assuming file inv.ext exist, the procedure for using 'sim2spice' is ext2sim inv sim2spice inv.sim Here's the resulting SPICE decks for SPICE3e... SPICE 3 Deck created from inv.sim, tech=edgaas * z2 3 4 2 efet1.2 2.8 C3 3 0 0.485F C4 4 0 1.062F z1 1 4 3 dfet1.2 2.8 * Commercial Plotting Service Artwork Conversion offers an IC plotting service. We will take your CIF/GDSII files and plot them in large format color using an HP 650C color plotter in 24 hrs at a very reasonable cost. Designers can FTP files to artwork.com and we will plot them the same day and return by FedEx. Fill patterns and line types are completely customizable although most users select from the 100 preset patterns already defined. Complete information, specifications and pricing is available from our Web site: <URL:http://www.artwork.com/plot1.html>. We are offering universities our best price that we give to high volume customers: $4.00 per square foot of plotted area. The plots can be any size (the plotter is 36 inches wide). We can of course be reached by tel (408) 426-6163 fax 426-2824. Foundries such as MOSIS, Chip Express and Orbit use this service as well as many small design shops that cannot justify a large format plotter. contact: Hagai Pettel hagai@artwork.com or Steve DiBartolomeo stevedb@artwork.com 3: Tips and tricks for magic (Version 6.3) Searching for nets: Yes, magic does actually let you search for node names. Use :specialopen netlist. Then click on the box underneath label, you will be prompted for the name of the label you want to search for. Enter the name, and then press enter twice. Click on show, and then find, magic will then highlight the net. Bulk node extraction: Problems with getting the bulk node to extract correctly? Try labeling the well with the node name that it is connected to. Painting Wells: Supposedly :cif in magic will automatically paint in the wells correctly. However this is not always the case. If you are using mosis 2u technol- ogy, and your wells are getting strange notches in them, you might try changing the grow 300 shrink 300 lines in your lambda=1.0(pwell) and lambda=1.0(nwell) cif sections of your tech file to grow 450 shrink 450. (Remember you can use :cif see CWN to see nwell, if :cifostyle is nwell, or :cif see CWP to see pwell if its pwell technology to preview what will be done with the well. You may use :feedback clear to erase what it shows you.) Magic notes available from ftp://gatekeeper.dec.com/pub/DEC/magic/notes (16.1.0.2): Magic note.1 - 9/14/90 - ANNOUNCEMENT: Magic V6 is ready Magic note.2 - 9/19/90 - DOC: Doc changes (fixed in releases after 9/20/90) Magic note.3 - 9/19/90 - GRAPHICS: Mode problem (fixed 9/20/90) Magic note.4 - 9/19/90 - HPUX: rindex macro for HPUX 7.0 and later Magic note.5 - 9/19/90 - GCC: "gcc" with magic, one user's experience Magic note.6 - 9/19/90 - FTP: Public FTP area for Magic notes Magic note.7 - 9/20/90 - RSIM: Compiling rsim, one user's suggestions & hints Magic note.8 - 9/26/90 - GENERAL: Magic tries to open bogus directories Magic note.9 - 9/26/90 - GRAPHICS: Mods to X11Helper Magic note.10 - 10/5/90 - DOS: Magic V4 for DOS and OS/2 Magic note.11 - 10/11/90 - GENERAL: reducing memory usage by 600k Magic note.12 - 12/19/90 - EXT2xxx: fixes bogus resistances Magic note.13 - 12/19/90 - EXTRESIS: fixed bug in resis that caused coredump. Magic note.14 - 12/19/90 - EXTRESIS: new version of scmos.tech for extresis Magic note.15 - 12/19/90 - TECH: documentation for contact line in tech file Magic note.16 - 12/19/90 - EXTRACT: bug fix to transistor attributes Magic note.17 - 5/13/91 - CALMA: Incorrect arrays in calma output Magic note.18 - 5/14/91 - CALMA: Extension to calma input Magic note.19 - 6/28/91 - IRSIM: Some .prm files for IRSIM Magic note.20 - 7/18/91 - EXTRESIS: fixes for Magic's extresis command Magic note.21 - 2/7/92 - FAQ: Frequently asked questions Magic note.22 - 11/6/91 - CALMA: how to write a calma tape Magic note.23 - 11/4/91 - EXT2xxx: fix for incorrect resistor extraction Magic note.24 - 11/8/91 - EXTRESIS: fix 0-ohm resistors Magic note.25 - 11/15/91 - NEXT: porting magic to the NeXT machine Magic note.26 - 11/21/91 - IRSIM: fix for hanging :decay command Magic note.27 - 12/17/91 - RESIS: fix for "Attempt to remove node ..." error Magic note.28 - 1/28/92 - MAGIC: anonymous FTP now available Magic note.29 - 3/27/92 - PLOT: support for Versatec 2700 Magic note.30 - 4/8/92 - PATHS: Have the ":source" command follow a path Magic note.31 - 4/10/92 - MPACK: Mpack now works with Magic 6.3 Magic note.32 - 3/13/92 - AED: Using AED displays with Magic 6.3 Magic note.33 - 3/13/92 - OPENWINDOWS: Compilation for OpenWindows/X11 Magic note.34 - 2/14/92 - OPENWINDOWS: fix mouse problem Magic note.35 - 8/27/92 - RS6000: diffs to get magic to run on RS6000 4: What can I use to do good plots from magic/CIF? (Thanks to Douglas Yarrington <arri@ee.eng.ohio-state.edu> and Harry Langenbacher <harry@neuronz.Jpl.Nasa.Gov>, for feedback here.) CIF: CIF stands for CalTech Intermediate Form. It's a graphics language which can be used to describe integrated circuit layouts. (from Jeffrey C. Gealow <jgealow@mtl.mit.edu>) The definitive description of the Caltech Intermediate Form (CIF Version 2.0) is included in Mead and Conway's book: @book{mead80, author = "Carver A. Mead and Lynn A. Conway", title = "Introduction to {VLSI} Systems", publisher = "Addison-Wesley", address = "Reading, Massachusetts", year = 1980, call = "TK7874.M37", A brief description is included in Rubin's book: @book{rubin87, author = "Steven M. Rubin", title = "Computer Aids for {VLSI} Design", publisher = "Addison-Wesley", address = "Reading, Massachusetts", year = 1987, call = "TK7874.R83", isbn = "0-201-05824-3"} Rubin's description should not be considered authoritative. Parts of the description are not accurate. cif2ps version 2 (Gordon W. Ross, MITRE): A much better version of cif2ps, extending the code of cif2ps (Marc Lesure, Arizona State University) and cifp (Arthur Simoneau, Aerospace Corp). It features command line options for depth and formatting. Can extend one plot over several pages (up to 5 by 5, or 25 pages). By default, uses a mixture of postscript gray fill and cross-hatching. Options include rotating the image, selecting the hierarchy depth to plot, and plotting style customization. Plots are in B/W only. It was posted to comp.sources.misc, and is available by ftp from ftp://ftp.uu.net/usenet/comp.sources.misc/volume8/cif2ps.Z (192.48.96.9). cifplot: Cifplot plots CIF format files on a screen, printer or plotter. Cifplot reads the .cif file, generates a b/w or color raster dump, and sends it to the printer. Plots can be scaled, clipped, or rotated. Hierarchy depth is selectable, as well as the choice of colormap or fill pattern. An option exists which will compress raster data to reduce the required disk space. For those plotting to a Versatec plotter, there is also a printer filter/driver available called vdmp. oct2ps (available as part of the octtools distribution): It is possible to convert your .mag file to octtools, and then you may use oct2ps to print it. Both cif2ps and oct2ps work well for conversion to postscript. They do look slightly different, so pick your favorite. Note that cif2ps can be converted to adobe encapsulated postscript easily by adding a bounding box comment. oct2ps does convert to color postscript, which can be a plus for those of you with color postscript printers. Flea: Flea ([F]un [L]oveable [E]ngineering [A]rtist) is a program used to plot magic and cif design files to various output devices. Parameters are passed to flea through the flags and flag data or through .flearc files and tech files. Supports: HP7580 plotter, HP7550 hpgl file output, HP7550 plotter lpr output, Postscript file output, Laser Writer lpr out- put, Versatec versaplot random output. Options include: Does line draw- ings with crosshatching for postscript, versatec, and hp plotters. Many options (depth, label depth, scale, path, format...) Available by ftp from ftp://zeus.ee.msstate.edu/pub/ . pplot: Can output color PostScript from CIF files. The source is available from: ftp://anise.ee.cornell.edu/pub/cad/ . It only generates PS files (including color PS), and there's no support for EPS files. It is limited in its support of cif commands. (Wire, roundflash, and delete are not supported.) It only supports manhattan geometry (Polygons and rotations may only be in 90 degree multiples.) vic: Part of the U. of Washington's Northwest Lab, for Integrated Systems Cad Tool Release (previously UW/NW VLSI Consortium). Does postscript and HP pen plotters. Only available as part of the package. CIF/Magic -> EPS -> groff/latex Currently no prgram here directly generates EPS files. It is possible to add an EPS bounding box (%% BoundingBox: l t b r) to the output from these programs to get an EPS file. Alternatively, ps2eps or ps2epsf may be used. CIF display on PCs LaSy (from Frank Bauernoeppel <bauernoe@informatik.hu-berlin.de>) The primary goal of LaSy was to implement a simple CIF layout viewer under MS-Windows. Requirements: MS-Windows 3.1 in extended mode or Windows-NT. Hi-resolution colour display, mouse, and a colour-printer are recommended. Note that there is a special Windows-NT version of LaSy included: lasy32.exe featuring 32- bit integer coordinates. Input: A CIF file plus appropriate layer description (.lay file). Sample layer descriptions are included. You probably have to adapt them to your tech- nology. CIF description see "Introduction to VLSI systems" by Mead and Conway. Several restrictions apply (cf. online help). Output: A layout window for visual inspection/measurements of the layout. Printer output using Windows printing mechanism, works fine. Clipboard copy in bitmap and metafile format. The metafile is a flat, object oriented layout representation understood by many applications. Can be postprocessed with MSDraw among others. The bitmap gives a pixel oriented view of the layout (at screen resolution) and can be postpro- cessed by most "Painting programs". I have repacked the archive for distribution (some designs removed). The new url is: <URL:ftp://ftp.informatik.hu- berlin.de/pub/local/hulda/lasy25.zip> Two references that describe the CIF file formats are: Introduction to VLSI Systems, Mead & Conway, 1980, p115 and Basic VLSI Design, Pucknell & Eshraghian, 1988, p 275 5: What tools are used to layout verification? Gemini: Gemini is a graph isomorphism tool for comparing circuit wirelists. The latest version of Gemini is 2.7 and is now available by FTP from shrimp.cs.washington.edu (128.95.1.99). Note: Gemini is not available by anonymous FTP. Send email to Larry McMurchie (larry@cs.washington.edu) if you need the FTP login and password for Gemini. Version 2.7 includes a new SIM file format to support four-terminal MOS transistors. This format is called 'LBL' and was inspired by Mario Aranha at Lawrence Berkeley Labs. Also some minor bugs have been fixed concerning portability. The user guide 'gemuser.ps' has been updated to reflect the changes to the code. Gemini compiles and runs on a wide variety of architectures, including Sparc, Mips, DEC AXP, HP, KSR, Intel i860, MC 68020 and VAX, under both Classic C and ANSI C compliant compilers. As the number of architectures continues to expand, new portability problems are revealed. Please keep us informed if you encounter any portability problems or bugs. Contact: Larry McMurchie Computer Science Department, FR-35 University of Washington Seattle, WA 98195 larry@cs.washington.edu Tanner LVS: This is a relatively inexpensive commercial product, see the section on Tanner tools. Wellchecker: (from MUG) ftp ftp.mosis.edu (128.9.0.32) netcmp: Part of the caltech tools (see the "Caltech VLSI CAD Tools" section) 6: EDIF data exchange format. (from Mark Lambert <lambert@cs.man.ac.uk>) The Electronic Design Interchange Format (EDIF) is the most widely used EDA standard and is used to interchange design data between CAD systems. The language is a standard under the auspices of the Electronic Indus- tries Association (the `EIA'), a US based industry association, responsi- ble for a number of electronics related standards. EDIF Version 3 0 0, used for the transfer of connectivity and schematic information, has also become an IEC standard; IEC 1690. The latest version of EDIF, Version 4 0 0, promises to add to EDIF Ver- sion 3 0 0 in the areas of; PCB and MCM Capabilities, Technology Rules and Manufacturing Drawings EDIF Version 4 0 0 is currently out for ballot, until 28th May 1996, as EDIF Version 3 9 9. EDIF Version 3 9 9 documentation is supplied in CD-ROM form or on paper directly from the EIA or Framemaker4 hypertext format directly from the EDIF Technical Centre, on behalf of the EIA. To review the material, the FrameViewer software is required. To obtain a copy of EDIF Version 3 9 9 (4 0 0), contact either Patti Rusher of the EIA or the EDIF Technical Centre for detailed instructions. The EDIF Version 2 0 0 Reference Manual and User Guides and copies of the manuals or CD-ROM for EDIF Version 3 0 0 can be obtained from the Elec- tronic Industries Association, Attn. Patti Rusher. For more EDIF related information visit the EDIF Web site: http://www.edif.org/ and the anonymous ftp server: ftp://edif.cs.man.ac.uk/pub/ An ftpmail server is provided for those without ftp access. Send an empty email message to: ftpmail@cs.man.ac.uk ; a message describing the com- mands which can be used in further email messages to retreive files will be sent to you. An electonic mailing list is available to people interested in EDIF and for EDIF developers/programmers. Send email to edif-users- request@cs.man.ac.uk to be added. Patti Rusher at the EIA can be contacted at: Patti Rusher 2500 Wilson Boulevard, Suite 203 Arlington, VA 22201, U.S.A. Telephone: +1 703 907 7545 Fax: +1 703 907 7501 E-mail: pattir@eia.org The EDIF Technical Centre can be contacted at: EDIF Technical Centre, Department of Computer Science, University of Manchester, Manchester M13 9PL, UK Tel: +44 161 275 6289 FAX: +44 161 275 6280 E-mail: edif-support@cs.man.ac.uk URL: http://www.cs.man.ac.uk/cad/EDIFTechnicalCentre/ 7: What layout examples are available? From MUG: Analog neural network library of cells, 66-bit Manchester carry-skip adder, static ram fabricated at 2-micron, an analog op amp, from ftp://ftp.mosis.edu/pub/mug . 8: How can I get my lsi design fabbed and how much will it cost? See section on mosis fabrication services as well. (From MUG 20 George Lewicki of Orbit Semiconductor) Orbit Semiconductor operates an integrated circuit prototyping service that accepts designs each week for all of its processes. The service is available to both U.S. and non-U.S. designers. In- quiries about the FORESIGHT prototyping service should be ad- dressed to George Lewicki. Designs can now be submitted directly via email. Orbit Semiconductor, Inc. 1215 Bordeaux Drive Sunnyvale, CA 94089 TEL: (408)-744-1800 FAX: (408)-747-1263 Email: foresight@orbsemi.com (Contributed by Don Bouldin of the University of Tennessee) Recently, I contacted several foundries to determine which com- panies are interested in fabricating small to moderate lots of wafers for cus- tom CMOS designs. I believe many of the readers of this column are designers who wish to have fabricated only 1,000 to 20,000 parts per year. There are currently several prototyp- ing services (e.g. MOSIS and Orbit) that can produce fewer than 100 parts for about $100 each and there are also several foun- dries which are willing to produce 100,000 custom parts for $5- $20 each (depending on the die size and yield). My purpose was to identify those companies filling the large gap between these two services. The prices in the table below are a result of averaging the data sup- plied by four foundries. The raw data varied by more than +/- 40% so the information should be used only in the early stages of budgetary plan- ning. Once the design specifications are fairly well known, the designer should contact one or more foundries to obtain specific budgetary quotes. As the design nears comple- tion, binding quotes can then be obtained. The following assumptions were made by the foundries: All designs will require custom CMOS wafer fabrication using a double-metal, single-poly process with a feature size between 2.0 and 1.2 microns. The designs may contain some analog circuitry and some RAM so the yield has been calculated pessimistically. The dies will be pack- aged and tested at 1 MHz using a Sentry- type digital tester for 5-10 seconds per part. The customer will furnish the test vectors. Piece Price includes Wafer Fabrication+Die Packaging+Part Testing Size Package Quantity |1,000 | 5,000 | 10,000 | 20,000 |100,000 ----------------------------------------------------------------- 2 mm x 2 mm; 84 PLCC: | $ 27 | $ 6 | $ 5 | $ 4 | $ 3 | 5 mm x 5 mm; 84 PLCC: | $ 31 | $ 12 | $ 8 | $ 7 | $ 6 | 5 mm x 5 mm; 132 PGA: | $ 49 | $ 30 | $ 25 | $ 22 | $ 18 | 7 mm x 7 mm; 132 PGA: | $ 65 | $ 44 | $ 36 | $ 31 | $ 27 | Lithography charges: $ 20,000 - $ 40,000 Preferred Formats: GDS-II or CIF Tapes Additional charges for Second-Poly: $ 5,000 (This is from MUG 19, there is also a list of foundries that these prices were derived from. In the interested of saving space, I have ommitted the list. The list is available from MUG's ftp site included in MUG newsletter #19.) 9: Mosis fabrication services. (From Mosis) Information is available from mosis for pricing and fab schedules through an automatic email system: Mail to mosis@mosis.edu with the message body as follows: REQUEST: INFORMATION TOPIC: TOPICS REQUEST: END for general information and a list of available topics. If you need to contact a person at mosis, you may mail to mosis@mosis.edu with REQUEST: ATTENTION. Also anonymous ftp is available. ftp to ftp.mosis.edu. This is a dupli- cation of all files that are available from the mail server. (From MUG 20 Contributed by Don Bouldin of the University of Tennessee) Multi-project fabrication of BICMOS designs are already available to European universities via CMP and to Canadian universities via the Cana- dian Microelectronic Corporation. However, in the United States, the demand for BiCMOS fabrication via MOSIS has not been considered signifi- cant. MOSIS is currently planning to start offering 0.5-micron BiCMOS during the first quarter of 1994. This will have a core voltage operation of 3.3v and a clock frequency in the range of 220-250Mhz. MOSIS is interested in seeing if a larger demand exists in the community than expressed so far. If you would like to have BiCMOS available before 1994, please send a short note to mosis@mosis.edu (with a copy to bouldin@sun1.engr.utk.edu) using the following format. REQUEST: ATTENTION . . your message goes here . . REQUEST: END (From MUG 20 and Chris Donham of the University of Pennsylvania) Support for mosis technologies under Cadence Analog Artist 2.4 is avail- able as is from University of Pennsylvania. This includes DRC, LVS, EXT, and a beginner's guide. Currently they are working on support for Opus 4.2. The files supporting Artist 2.4 are currently available via anonymous FTP. Penn is not affiliated with MOSIS, except as a satisfied customer, and as a result, NO WARRANTY IS EXPRESSED OR IMPLIED WITH REGARDS TO THE FILES, OR THEIR FITNESS FOR ANY USE. Use the files at your own risk. To obtain the files, FTP to axon.ee.upenn.edu (130.91.6.208), using the name "anonymous" and your mailing address as the password. The files are in the "pub" directory. Penn is in the process of switching from Artist 2.4 to Opus 4.2. The manual is being rewritten, and the support files are being updated. Technology files supporting DRC, Extract, and Compare are currently in beta-test. If problems or bugs are detected, please send email to "cadence@axon.ee.upenn.edu". 10: Archive sites for comp.lsi.cad and comp.lsi (None of these are comprehensive archives, rather, they have about 3 postings each) comp.lsi.cad: ftp://cnam.cnam.fr/pub/Archives/comp.archives/auto/ ftp://cs.dal.ca/pub/comp.archives/ ftp://srawgw.sra.co.jp/.a/sranha-bp/arch/arch/comp.archives/auto/ 11: Other newsgroups and information sources that relate to comp.lsi* alt.cad comp.cad.cadence comp.lang.verilog comp.lang.vhdl comp.sys.mentor sci.electronics The following gopher link points to a collection of information from pulled from newsgroups like comp.lsi.cad, comp.lsi, and other cad related sources. gopher://kona.ee.pit.edu/ 12: Simulation programs tips/tricks/bugs Berkeley spice: Pspice: Hspice: If your simulation won't converge for a given DC input, you can ramp the input and print the DC operating point and then set the nodes that way for future simulations. A number of documents are available for information on BSIM model parame- ters: (from Mark Johnson, as posted to comp.lsi <mjohnson@netcom.com>) 1. The very best written description I have seen is in a software manual. The good news is that this manual is free; the bad news is that you have to buy the multi-thousand-dollar program in order to get the free manual. The program is HSPICE from Meta-Software Inc (Campbell, Calif., USA). The HSPICE User's Manual, chapter 7, gives all the details you'd ever want to know regarding BSIM parameters. 2. The second best description I have seen of BSIM is in, strangely enough, a manual for BSIM2 (!). It is available from the University of California at Berkeley. Telephone (510)-643-6687 and they will give you instructions on how to buy the manual. (They'll probably suggest that you might want to buy some software too). J.S. Duster, M.C. Jeng, P.K. Ko, and C. Hu, "Users Guide for the BSIM2 Parameter Extraction Program and the SPICE3 with BSIM Implementation" 3. You can learn some things about BSIM parameters by reading about pro- grams which extract the parameters from measured data. UC Berkeley offers several programs and manuals for this. The one that I person- ally prefer is M.C. Jeng, B.J. Sheu, and P.K. Ko: "BSIM Parameter Extraction - Algorithms and User's Guide," Memo No. UCB/ERL M85/79, 7 October 1985. 4. Next, look at Sheu's Ph.D. thesis. He is the guy who combined the Bell Labs CSIM model with a bunch of other published equations, and formulated BSIM. It's available from the same phone number. B.J. Sheu, "MOS Transistor Modelling and Characterization for Circuit Simulation", Memo No. UCB/ERL M85/85, 26 October 1985 5. The worst description (in +my+ opinion of course) is unfortunately in the most-accessible publication. To save space in the journal they left out some parameter discussions and (again in my opinion) produced a disjointed, not-fully- informative paper. Others may have different views, naturally. B.J. Sheu, D.L. Scharfetter, P-K Ko, M-C Jeng, "BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors," IEEE Journal of Solid-State Circuits, Vol SC-22, No. 4, August 1987, pp. 558-565. 13: Getting the latest version of the FAQ: Mail to lsi-faq-request@ece.ucdavis.edu with the subject "send faq". If you wish to be added to the FAQ mailing list, send a note to lsi-faq- request@ece.ucdavis.edu with subject heading 'subscribe'. You will then have the FAQ regularly emailed to the return address of the note. Like- wise, use the subject heading 'unsubscribe' to be removed from the list. This FAQ is now cross-posted to news.answers and comp.answers. This news- group is archived periodically on ftp://rtfm.mit.edu/pub/usenet/news.answers/ [18.181.0.24]. Postings are archived as "part1" through "part4". Our FAQ is also available through the WWW pages. You can access it at <URL:http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html> . I sug- gest this site above the one listed below, since ours is hyper-text for- matted and the site below is essentially just a text to html conversion with no table of contents. (from Thomas A. Fine <fine@cis.ohio-state.edu>) WWW I maintain an "archive" of news.answers available via WWW. As a matter of fact, I used WWW to read through your posting just last week. I found it very informative; thanks much. Advertise the following refer- ence to get to the archive in general: <URL:http://www.cis.ohio-state.edu:80/hypertext/faq/usenet/FAQ- List.html> or to get to your particular FAQ, give out this reference: <URL:http://www.cis.ohio-state.edu:80/hypertext/faq/usenet/lsi-cad- faq/top.html> Gopher The news.answers introduction (which I pulled up in WWW ;-) lists the following gopher sites for the FAQs: cc1.kuleuven.ac.be port 70 jupiter.sun.csd.unb.ca port 70 gopher.univ-lyon1.fr, port 70 ftp.win.tue.nl, port 70 gopher.win.tue.nl, port 70 kona.ee.pitt.edu 70 To reference gopher from Mosaic, us the following reference: gopher://kona.ee.pitt.edu WAIS I pulled this straight out of the news.answers Introduction: Note that the periodic posting archives on rtfm.mit.edu are also accessi- ble via WAIS (the database name is "usenet" on port 210). If you don't know what WAIS is, don't worry about it, although you can look in comp.infosystems.wais if you're curious. And don't write to us and ask, please; we unfortuately already have too many things to deal with without having to answer questions about other people's software. 14: Converting from/to GDSII/CIF/Magic Magic version 6.3 is capable of reading and writting to all three for- mats. (From the magic man page): calma [option] [args] This command is used to read and write files in Calma GDS II Stream for- mat (version 3.0, corresponding to GDS II Release 5.1). This format is like CIF, in that it describes physical mask layers instead of Magic layers. In fact, the technology file specifies a correspondence between CIF and Calma layers. The current CIF output style (see cif ostyle) con- trols how Calma stream layers are generated from Magic layers. (from Jeffrey C. Gealow <jgealow@mtl.mit.edu>) Calma Company sold their electronics CAD/CAM software (GDS II) to Valid Logic Systems which later merged with Cadence. Cadence has added a few extensions. A Cadence document is almost identi- cal to the old Calma Company document: Cadence Design Systems, Inc. Construct Stream Format Reference Version 4.0 August 1991 900-001094 An overview of the Stream format is included in Rubin's book: @book{rubin87, author = "Steven M. Rubin", title = "Computer Aids for {VLSI} Design", publisher = "Addison-Wesley", address = "Reading, Massachusetts", year = 1987, call = "TK7874.R83", isbn = "0-201-05824-3"} cif [option] [args] Read or write files in Caltech Intermediate Form (CIF). 15: CFI (CAD Framework Initiative Inc.) (From Randy Kirchhof <rkk@cfi.org>) CFI quick FAQ guide for release 1.0, v1.1 For those of you who may be unfamiliar with our work, The CAD Framework Initiative Inc. was formed in May 1988. We're located in Austin, TX, although we're a distributed company. We're a not-for-profit consortium formed under the laws of the state of Delaware. Our mission is to pro- vide industry-accepted standards and technology that enable interopera- bility of electronic design automation (EDA) applications and data for end-users and suppliers world-wide. This includes interoperability between EDA applications as well as the integration of EDA applications into CAD frameworks. A CAD framework is a software infrastructure which provides a common operating environment for CAD tools. Through a framework, a user should be able to launch and manage tools, create, organize, and manage data, graphically view the entire design process and perform design management tasks such as configuration management, version management, etc. CFI Release 1.0 started shipping in January 1993. Q When can users buy CFI compliant tools? A Eleven vendor companies have announced EDA products and frameworks which will be available and compliant with CFI 1.0 standards. CFI has initiated a formal certification program for these (and future products) as of 12/93. CFI expects to begin awarding the first certification brand marks in the first quarter of 1994. We expect to see a rapid expansion of compliant products beginning in the third quarter of 1994. Q How can the Standards be obtained? Are there any restrictions? A The 1.0 Standards, copyrighted by CFI, are available to members and non-members priced as a set or individually through CFI Member Services (512) 338-3739. They will also being distributed under license by Cadence, Mentor Graphics, and Viewlogic as part of their product documentation. Versions of the 1.0 Standards are available on diskette in an electronic format as well as bound manuals. Q How do the CFI Standards relate to vendor framework programs like Mentor's Open Door, Viewlogic Power Team and Cadence Connection Partners - with so many point tool vendors participating, don't they have this problem solved? A The major EDA vendors have been and continue to be challenged by their customers over multi-vendor integration. These programs were a practical response by opening up their existing interfaces and providing services to assist integration. CFI 1.0, and future releases, will create a functional alternative to a growing subset of those interfaces so that the requirement that point tool ven- dors create partnership specific versions of their tool will decrease. Actually, the service provided through these programs will likely compliment the CFI certification effort as these supplier's frameworks become fully certified. Contact: cfi@cfi.org (CFI Member Services, Jean Gallagher) CFI Main number: (512) 338-3739 Fax: (512) 338-3853 16: What synthesis systems are there? Thanks to Simon Leung <sleung@sun1.atitech.ca>, Michel Berkelaar <michel@ele.tue.nl>, Noritake Yonezawa <yonezawa@cs.uiuc.edu>, Donald A Lobo <lobo@guardian.cs.psu.edu>, Greg Ward <gregw@bnr.ca>, Peter Duzy, Robert Walker <walkerb@turing.cs.rpi.edu>, Heinrich Kraemer <kraemer@fzi.de>, Luciano Lavagno <luciano@ic.eecs.berkeley.edu> ADPS - Case Western Reserve University, USA - scheduling and data path allocation - Papachristou, C.A. et al.: "A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm", Proc. of the 27th DAC, pp. 77-83, June 1990. ALPS/LYRA/ARYL - Tsing Hua University - scheduling and data path allocation - Lee, J-H: et al.: "A New Integer Linear Programming Formulation of the Scheduling Problem in Data Path Synthesis", Proc. of ICCAD89, pp. 20-23, November 1989. BDSYN - University of California, Berkeley, USA - FSM synthesis from DECSIM language for multilevel combination-logic realization - Brayton, R.: "Multiple-level Logic Optimization System", Proc. of IEEE ICCAD, Santa Clara, Nov. 1986 BECOME - AT & T Bell Labs, USA - FSM synthesis from C-like language for PLA, PLD and standard cell realization - Wei, R-S.: "BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping", Proc. of 25th ACM/IEEE Design Automation Conference, pp. 409-414, IEEE, 1988 BOLD - logic optimization - Bartlett, K. "Synthesis and Optimization of Multilevel Logic Under Timing Constraints", IEEE Transactions on Computer-Aided Design, Vol 5, No 10, October 1986 BRIDGE - AT & T Bell Labs, USA - High-level synthesis FDL2-language descriptions - Tseng: "Bridge: A Versatile Behavioral Synthesis System", Proc. of 25th ACM/IEEE Design Automation Conference, pp. 415-420, IEEE, 1988 User Contributions: |
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