Tools for Sound Processing
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ARES/MARS workstation
X20 processor
ALU
MUL
data flow
are operated [108]. SMS comes with a very appealing graphical interface under
Microsoft Windows, with a web-based interface, and is available as a command-
line program for other operating systems, such as the various flavors of unix.
SMS uses an implementation of the Spectral Description Interchange Format
which could potentially be used by other packages operating transformations
based on the STFT. As an example, consider the following SMS synthesis
score which takes the results of analysis and resynthesizes with application of a
pitch-shifting envelope and an accentuation of inharmonicity:
InputSmsFile march.sms
OutputSoundFile exroc.snd
FreqSine 0 1.2 .5 1.1 .8 1 1 1
FreqSineStretch 0.2
B.5
Structure of a Digital Signal Processor
In this section we examine the ARES/MARS workstation as a prototypical case
of hardware/software systems dedicated to digital audio processing. Namely, we
explain the internal arithmetics of the X20 processor, the computational core of
the workstation, and the memory management system.
We have mentioned that the ARES/MARS workstation uses an expansion
board divided into two parts: a control part based on the microcontroller Mo-
torola MC68302, and an audio processing part based on two proprietary X20
processors. The X20 processor runs, for each audio cycle, a 512-instruction mi-
croprogram, contained in a static external memory. Each microinstruction is 64
bits long, and it is computed in a 25ns machine cycle. Multiplying this cycle by
the 512 instructions we get the working sampling rate of the machine, that is
F
s
= 39062.5Hz.
A rough scheme of the X20 processor is shown in figure 10, where we can
notice three units:
· Functional Unit: adder (ALU), multiplier (MUL), registers (RM), data
busses (C and Z);
· Data Memory Unit: data memories DMA and DMB, data busses (A,
B, and W);
· Control Unit: addresses of data memories (ADR), access to external
memory (FUN), connection to DAC/ADC audio bus, connection to mi-
croprogram memory and microcontroller (not shown in figure 10).
The computations are based on a circular data flow that involves the data
memories and the functional unit. The presence of two data memories and one
functional unit allows a parallel organization of microprograms. The data flow
can be divided into four phases:
· Data gathering from memories DMA, DMB, or external memory (FUN);
· Selection of input data for the functional unit;
· Data processing by the functional unit;
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