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NY R02356

August 15, 2005

CLA-2-85:RR:NC:MM:109 R02356


TARIFF NO.: 8542.21.8089

Mr. Michael E. Roll
Pisani & Roll
Attorneys at Law
1875 Century Park East, Suite 600
Los Angeles, CA 90067

RE: The tariff classification of a Prestera and Alaska Integrated Circuits from an unspecified country

Dear Mr. Roll:

In your letter dated August 1, 2005, you requested a tariff classification ruling on behalf of your client, Marvel Semiconductor, Inc. (“Marvel”).

The merchandise subject to this ruling is Marvell’s Prestera packet processors identified by part numbers prefixes 98EX, 98FX, and 98 MX and Marvell’s Alaska transceivers identified by part number prefixes 88X and 88E.

The Prestera packet processors identified by part numbers prefixes 98EX, 98DX, 98FX, and 98MX are members of the Prestera family of single-chip packet switch processors. They are used in networks to integrate Gigabit MAC ports or a 10GBASE-X transceiver port, a switching engine, and a highly flexible 10 Gbps expansion bus. The 98EX, 98DX, 98FX, and 98MX are complete system on chip (“SoC”) integrated circuit devices that support full-wire speed L2 bridging, L3 routing, comprehensive IP (Internet protocol) multicast support and L2-L5 advanced traffic classification filtering, and prioritization.

These packet processors do not execute any code, but rather perform their function by implementation of state-machines that perform specific hard-wired functions. The digital design process used in the implementation of these chips follows common practices of digital design, where an engineer would typically write a state-machine description in Verilog (a design language) and then use off-the-shelf tools to synthesize the code into gates and transistors. The transistors and their interconnects are implemented by a fabrication facility using the CMOS “Complementary Metal Oxide Semiconductor” manufacturing process with silicon as the substrate material. CMOS is a digital process. The packet processors also contain SRAM (Static Random Access Memory) blocks, which total over 2Mbit. The SRAM is used by internal state-machines in order to perform functions like bridging and routing of packets that are received through the chip ports. The SRAM is part of the silicon die and is manufactured together with the rest of the chip transistors.

The Alaska transceivers identified by part number prefixes 88X and 88E are fully integrated single chip devices that perform all the physical layer functions for 10 Gigabit Ethernet and 10 Gigabit Fiber Channel LAN PHY (Local Area Network Physical) and WAN PHY (Wide Area Network Physical) applications, delivering high speed bi-directional point-to-point data transmissions to provide up to 20 Gbps of full duplex data transmission capacity of fiber medium. These items support the 10 Gigabit Attachment Unit Interface.

These Alaska transceivers are manufactured using a CMOS manufacturing process with silicon as the substrate material. CMOS is a digital process. They do not execute any code and contain less than 0.5 Mbit of SRAM.

Neither the Prestera packet processors nor the Alaska transceivers contain volatile memory, transistor-transistor logic (TTL) or emitter-coupled logic (ECL), nor are they microprocessors.

The applicable subheading for the Prestera packet processors (part numbers prefixes 98EX, 98DX, 98FX, and 98MX) and the Alaska transceivers (part number prefixes 88X and 88E) will be 8542.21.8089, Harmonized Tariff Schedule of the United States (HTS), which provides for “Electronic integrated circuits and microassemblies: parts thereof: Monolithic integrated circuits: Digital: Other: Other: Silicon: Other, Other: Other.” The rate of duty will be free.

This ruling is being issued under the provisions of Part 177 of the Customs Regulations (19 C.F.R. 177).

A copy of the ruling or the control number indicated above should be provided with the entry documents filed at the time this merchandise is imported. If you have any questions regarding the ruling, contact National Import Specialist Linda M. Hackett at 646-733-3015.


Robert B. Swierupski

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