Top Inventors for class "Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)" |
Rank | Inventor's name | Country | City/State | Last publication | # of patent apps in this class |
1 | Michael K. Gschwind | US | Chappaqua, NY | Apr 16, 2020 / 20200117360 - AUTOMATIC PINNING OF UNITS OF MEMORY | 106 |
2 | Timothy J. Slegel | US | Staatsburg, NY | Oct 17, 2019 / 20190317768 - GUARDED STORAGE EVENT HANDLING DURING TRANSACTIONAL EXECUTION | 84 |
3 | Elmoustapha Ould-Ahmed-Vall | US | Chandler, AZ | Sep 15, 2022 / 20220291927 - SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE | 75 |
4 | Robert Valentine | IL | Kiryat Tivon | Sep 15, 2022 / 20220291927 - SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE | 66 |
5 | G. Glenn Henry | US | Austin, TX | Jun 07, 2018 / 20180157970 - PROCESSOR WITH MEMORY ARRAY OPERABLE AS EITHER CACHE MEMORY OR NEURAL NETWORK UNIT MEMORY | 62 |
6 | Jeffry E. Gonion | US | Campbell, CA | Jan 26, 2017 / 20170024559 - MARKING VALID RETURN TARGETS | 60 |
7 | Terry Parks | US | Austin, TX | Dec 29, 2016 / 20160380649 - HARDWARE DATA COMPRESSOR USING DYNAMIC HASH ALGORITHM BASED ON INPUT BLOCK TYPE | 59 |
8 | Valentina Salapura | US | Chappaqua, NY | Apr 16, 2020 / 20200117360 - AUTOMATIC PINNING OF UNITS OF MEMORY | 55 |
9 | Dan F. Greiner | US | San Jose, CA | Oct 17, 2019 / 20190317768 - GUARDED STORAGE EVENT HANDLING DURING TRANSACTIONAL EXECUTION | 51 |
10 | Chung-Lung K. Shum | US | Wappingers Falls, NY | Oct 17, 2019 / 20190317768 - GUARDED STORAGE EVENT HANDLING DURING TRANSACTIONAL EXECUTION | 50 |
11 | Bret L. Toll | US | Hillsboro, OR | Sep 15, 2022 / 20220291927 - SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE | 50 |
12 | Brian R. Prasky | US | Wappingers Falls, NY | Jul 30, 2015 / 20150212858 - MANAGEMENT OF RESOURCES WITHIN A COMPUTING ENVIRONMENT | 48 |
13 | Jonathan D. Bradbury | US | Poughkeepsie, NY | Sep 01, 2022 / 20220276866 - VECTOR PACK AND UNPACK INSTRUCTIONS | 47 |
14 | Eric M. Schwarz | US | Gardiner, NY | Aug 20, 2020 / 20200267001 - COMPUTE DIGITAL SIGNATURE AUTHENTICATION SIGN INSTRUCTION | 42 |
15 | James J. Bonanno | US | Wappingers Falls, NY | Jun 15, 2017 / 20170168828 - PERCEPTRON BRANCH PREDICTOR WITH VIRTUALIZED WEIGHTS | 39 |
16 | Fadi Y. Busaba | US | Poughkeepsie, NY | Jan 06, 2022 / 20220004499 - HOST VIRTUAL ADDRESS SPACE FOR SECURE INTERFACE CONTROL STORAGE | 39 |
17 | Martin G. Dixon | US | Portland, OR | Nov 25, 2021 / 20210365264 - ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS | 38 |
18 | Rodney E. Hooker | US | Austin, TX | Jun 09, 2016 / 20160162293 - ASYMMETRIC PROCESSOR WITH CORES THAT SUPPORT DIFFERENT ISA INSTRUCTION SUBSETS | 37 |
19 | Charles W. Gainey, Jr. | US | Poughkeepsie, NY | Oct 17, 2019 / 20190317828 - EXECUTION OF AN INSTRUCTION FOR PERFORMING A CONFIGURATION VIRTUAL TOPOLOGY CHANGE | 31 |
20 | Vinodh Gopal | US | Westborough, MA | Aug 18, 2022 / 20220263770 - APPLICATION-TO-APPLICATION RESOURCE RESERVATION SCHEMES FOR PRECISION NETWORKING | 31 |
21 | Mark S. Farrell | US | Pleasant Valley, NY | Jan 14, 2021 / 20210011719 - SORT AND MERGE INSTRUCTION FOR A GENERAL-PURPOSE PROCESSOR | 29 |
22 | Lucian Codrescu | US | Austin, TX | Feb 16, 2017 / 20170046156 - TABLE LOOKUP USING SIMD INSTRUCTIONS | 29 |
23 | International Business Machines Corporation | US | | Jun 09, 2016 / 20160164774 - SET UP OF DIRECT MAPPED ROUTERS LOCATED ACROSS INDEPENDENTLY MANAGED COMPUTE AND STORAGE NETWORKS | 29 |
24 | Christian Jacobi | US | Poughkeepsie, NY | Mar 19, 2020 / 20200089493 - MICROPROCESSOR INCLUDING AN EFFICIENCY LOGIC UNIT | 29 |
25 | Zeev Sperber | IL | Zichron Yackov | Sep 15, 2022 / 20220291927 - SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE | 28 |
26 | Mark J. Charney | US | Lexington, MA | Sep 15, 2022 / 20220291927 - SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE | 27 |
27 | Benny Eitan | IL | Haifa | Jul 13, 2017 / 20170199726 - MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS | 26 |
28 | Christopher J. Hughes | US | Santa Clara, CA | Jul 28, 2022 / 20220237123 - APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE | 26 |
29 | Amit Gradstein | IL | Binyamina | Jun 30, 2022 / 20220207107 - APPARATUS AND METHOD FOR COMPLEX MATRIX MULTIPLICATION | 25 |
30 | Brett Olsson | US | Cary, NC | Jan 06, 2022 / 20220004386 - COMPUTE ARRAY OF A PROCESSOR WITH MIXED-PRECISION NUMERICAL LINEAR ALGEBRA SUPPORT | 25 |
31 | Paul E. Schardt | US | Rochester, MN | Mar 19, 2020 / 20200089540 - COALESCING MULTIPLE ACCELERATORS INTO A SINGLE ACCELERATOR | 25 |
32 | Balaram Sinharoy | US | Poughkeepsie, NY | Oct 15, 2015 / 20150293855 - PAGE TABLE INCLUDING DATA FETCH WIDTH INDICATOR | 24 |
33 | Marcel Mitran | CA | Markham | Oct 17, 2019 / 20190317765 - CONDITIONAL TRANSACTION END INSTRUCTION | 24 |
34 | William C. Moyer | US | Dripping Springs, TX | May 26, 2016 / 20160147660 - ACCESS EXTENT MONITORING FOR DATA TRANSFER REDUCTION | 24 |
35 | Matthew R. Tubbs | US | Rochester, MN | Jul 25, 2013 / 20130191825 - VIRTUALIZATION SUPPORT FOR SAVING AND RESTORING BRANCH PREDICTION LOGIC STATES | 24 |
36 | Dung Q. Nguyen | US | Austin, TX | Nov 04, 2021 / 20210342150 - PROCESSOR PROVIDING INTELLIGENT MANAGEMENT OF VALUES BUFFERED IN OVERLAID ARCHITECTED AND NON-ARCHITECTED REGISTER FILES | 24 |
37 | International Business Machines Corporation | US | Armonk, NY | Sep 18, 2014 / 20140282563 - DEPLOYING PARALLEL DATA INTEGRATION APPLICATIONS TO DISTRIBUTED COMPUTING ENVIRONMENTS | 24 |
38 | Martin Vorbach | DE | Lingenfeld | Dec 30, 2021 / 20210406027 - ADVANCED PROCESSOR ARCHITECTURE | 24 |
39 | David A. Luick | US | Rochester, MN | Aug 16, 2012 / 20120210107 - PREDICATED ISSUE FOR CONDITIONAL BRANCH INSTRUCTIONS | 23 |
40 | Jesus Corbal | ES | Barcelona | Jul 07, 2022 / 20220215117 - INSTRUCTION EXECUTION THAT BROADCASTS AND MASKS DATA VALUES AT DIFFERENT LEVELS OF GRANULARITY | 23 |
41 | Charles J. Archer | US | Rochester, MN | Mar 19, 2015 / 20150081985 - ADMINISTERING INTER-CORE COMMUNICATION VIA SHARED MEMORY | 23 |
42 | Gilbert M. Wolrich | US | Framingham, MA | Nov 25, 2021 / 20210365264 - ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS | 22 |
43 | Brian Michael Stempel | US | Raleigh, NC | Dec 31, 2020 / 20200409712 - OPERAND-BASED REACH EXPLICIT DATAFLOW PROCESSORS, AND RELATED METHODS AND COMPUTER-READABLE MEDIA | 22 |
44 | Hung Q. Le | US | Austin, TX | Jun 15, 2017 / 20170168945 - HANDLING UNALIGNED LOAD OPERATIONS IN A MULTI-SLICE COMPUTER PROCESSOR | 22 |
45 | Keith E. Diefendorff | US | Los Gatos, CA | Dec 13, 2012 / 20120317441 - NON-FAULTING AND FIRST FAULTING INSTRUCTIONS FOR PROCESSING VECTORS | 21 |
46 | Michael Karl Gschwind | US | Chappaqua, NY | Sep 14, 2017 / 20170262283 - INDEPENDENT VECTOR ELEMENT ORDER AND MEMORY BYTE ORDER CONTROLS | 21 |
47 | Robert A. Shearer | US | Rochester, MN | Jul 25, 2013 / 20130191825 - VIRTUALIZATION SUPPORT FOR SAVING AND RESTORING BRANCH PREDICTION LOGIC STATES | 21 |
48 | Anthony Saporito | US | Highland, NY | Jan 13, 2022 / 20220012159 - HETEROGENEOUS SERVICES FOR ENABLING COLLABORATIVE LOGIC DESIGN AND DEBUG IN ASPECT ORIENTED HARDWARE DESIGNING | 21 |
49 | James Norris Dieffenderfer | US | Apex, NC | Oct 14, 2021 / 20210318884 - PROVIDING EXCEPTION STACK MANAGEMENT USING STACK PANIC FAULT EXCEPTIONS IN PROCESSOR-BASED DEVICES | 21 |
50 | Alexandre E. Eichenberger | US | Chappaqua, NY | Nov 17, 2016 / 20160335087 - OPTIMIZING BRANCH RE-WIRING IN A SOFTWARE INSTRUCTION CACHE | 21 |
51 | James D. Guilford | US | Northborough, MA | Jul 14, 2022 / 20220224353 - METHODS AND APPARATUS TO PARALLELIZE DATA DECOMPRESSION | 20 |
52 | Dong-Hoon Yoo | KR | Seoul | Feb 20, 2014 / 20140052960 - APPARATUS AND METHOD FOR GENERATING VLIW, AND PROCESSOR AND METHOD FOR PROCESSING VLIW | 20 |
53 | Sean P. Mirkes | US | Beaverton, OR | Nov 25, 2021 / 20210365264 - ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS | 20 |
54 | Ravi K. Arimilli | US | Austin, TX | Jul 11, 2013 / 20130179899 - MANAGEMENT OF PROCESS-TO-PROCESS COMMUNICATION REQUESTS | 20 |
55 | Wajdi K. Feghali | US | Boston, MA | Nov 25, 2021 / 20210365264 - ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS | 20 |
56 | Bernhard Egger | KR | Seoul | May 29, 2014 / 20140149968 - DYNAMIC LIBRARY PROFILING METHOD AND DYNAMIC LIBRARY PROFILING SYSTEM | 20 |
57 | Elmoustapha Ould-Ahmed Vall | US | Phoenix, AZ | Jun 30, 2016 / 20160188532 - METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE | 20 |
58 | Donald W. Schmidt | US | Stone Ridge, NY | Jan 14, 2021 / 20210011719 - SORT AND MERGE INSTRUCTION FOR A GENERAL-PURPOSE PROCESSOR | 20 |
59 | Adam J. Muff | US | Rochester, MN | Jul 25, 2013 / 20130191825 - VIRTUALIZATION SUPPORT FOR SAVING AND RESTORING BRANCH PREDICTION LOGIC STATES | 19 |
60 | Erdinc Ozturk | US | Marlborough, MA | Nov 25, 2021 / 20210365264 - ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS | 19 |
61 | Khary J. Alexander | US | Poughkeepsie, NY | Jun 15, 2017 / 20170171197 - END-TO-END PROTECTION FOR SHROUDED VIRTUAL SERVERS | 19 |
62 | Gerald George Pechanek | US | Cary, NC | Feb 05, 2015 / 20150039856 - Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture | 19 |
63 | Larry M. Mennemeier | US | Boulder Creek, CA | Oct 03, 2013 / 20130262836 - PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA | 18 |
64 | Mohammad Abdallah | US | San Jose, CA | Sep 14, 2017 / 20170262287 - SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH PREDICTION | 18 |
65 | Christopher M. Abernathy | US | Austin, TX | Sep 11, 2014 / 20140258691 - THREAD TRANSITION MANAGEMENT | 18 |
66 | Rodney Wayne Smith | US | Raleigh, NC | Oct 14, 2021 / 20210318905 - OPERAND POOL INSTRUCTION RESERVATION CLUSTERING IN A SCHEDULER CIRCUIT IN A PROCESSOR | 18 |
67 | Youfeng Wu | US | Palo Alto, CA | Dec 29, 2016 / 20160378679 - TECHNOLOGIES FOR POSITION-INDEPENDENT PERSISTENT MEMORY POINTERS | 18 |
68 | Gregory W. Alexander | US | Pflugerville, TX | Dec 29, 2016 / 20160378489 - REGISTER FILE MAPPING | 18 |
69 | Matthew C. Merten | US | Hillsboro, OR | Nov 25, 2021 / 20210365264 - ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS | 17 |
70 | Michael Scott Mcilvaine | US | Raleigh, NC | Sep 08, 2022 / 20220283819 - PROCESSOR BRANCH PREDICTION CIRCUIT EMPLOYING BACK-INVALIDATION OF PREDICTION CACHE ENTRIES BASED ON DECODED BRANCH INSTRUCTIONS AND RELATED METHODS | 17 |
71 | Andrew T. Forsyth | US | Kirkland, WA | Dec 30, 2021 / 20210406026 - COALESCING ADJACENT GATHER/SCATTER OPERATIONS | 17 |
72 | Gerard M. Col | US | Austin, TX | Dec 03, 2015 / 20150347140 - PROCESSOR THAT LEAPFROGS MOV INSTRUCTIONS | 17 |
73 | Michael A. Blocksome | US | Rochester, MN | Oct 29, 2015 / 20150312330 - ADMINISTERING VIRTUAL MACHINES IN A DISTRIBUTED COMPUTING ENVIRONMENT | 17 |
74 | Craig Hansen | US | Los Altos, CA | Feb 18, 2016 / 20160048393 - PROCESSOR FOR EXECUTING WIDE OPERAND OPERATIONS USING A CONTROL REGISTER AND A RESULTS REGISTER | 17 |
75 | Christian Jacobi | DE | Schoenaich | Jun 30, 2016 / 20160188488 - STORING A SYSTEM-ABSOLUTE ADDRESS (SAA) IN A FIRST LEVEL TRANSLATION LOOK-ASIDE BUFFER (TLB) | 17 |
76 | Milind B. Girkar | US | Sunnyvale, CA | Sep 15, 2022 / 20220291927 - SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE | 16 |
77 | David S. Levitan | US | Austin, TX | Sep 14, 2017 / 20170262286 - BLOCKING INSTRUCTION FETCHING IN A COMPUTER PROCESSOR | 16 |
78 | Dung Quoc Nguyen | US | Austin, TX | Dec 30, 2021 / 20210406023 - PARALLEL SLICE PROCESSOR HAVING A RECIRCULATING LOAD-STORE QUEUE FOR FAST DEALLOCATION OF ISSUE QUEUE ENTRIES | 16 |
79 | Alexandre J. Farcy | US | Hillsboro, OR | May 12, 2016 / 20160132337 - Method, apparatus, and system for speculative abort control mechanisms | 16 |
80 | Robert T. Golla | US | Round Rock, TX | Feb 18, 2016 / 20160048187 - ADAPTIVE MICROPROCESSOR POWER RAMP CONTROL | 15 |
81 | Jason W. Brandt | US | Austin, TX | Jul 28, 2022 / 20220237123 - APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE | 15 |
82 | Alexia Massalin | US | San Jose, CA | Feb 18, 2016 / 20160048393 - PROCESSOR FOR EXECUTING WIDE OPERAND OPERATIONS USING A CONTROL REGISTER AND A RESULTS REGISTER | 15 |
83 | Alper Buyuktosunoglu | US | White Plains, NY | Aug 04, 2022 / 20220245397 - UPDATING OF STATISTICAL SETS FOR DECENTRALIZED DISTRIBUTED TRAINING OF A MACHINE LEARNING MODEL | 15 |
84 | Chung-Lung Kevin Shum | US | Wappingers Falls, NY | Jun 09, 2016 / 20160162410 - DEMOTE INSTRUCTION FOR RELINQUISHING CACHE LINE OWNERSHIP | 15 |
85 | Mohammad A. Abdallah | US | San Jose, CA | Nov 17, 2016 / 20160335130 - INTERCONNECT STRUCTURE TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES | 15 |
86 | Conrado Blasco Allue | US | Sunnyvale, CA | Feb 05, 2015 / 20150039860 - RDA CHECKPOINT OPTIMIZATION | 15 |
87 | Maxim Loktyukhin | US | Folsom, CA | May 21, 2015 / 20150143084 - HAND HELD DEVICE TO PERFORM A BIT RANGE ISOLATION INSTRUCTION | 15 |
88 | Tai-Song Jin | KR | Seoul | Jan 26, 2017 / 20170024216 - METHOD AND DEVICE FOR PROCESSING VLIW INSTRUCTION, AND METHOD AND DEVICE FOR GENERATING INSTRUCTION FOR PROCESSING VLIW INSTRUCTION | 14 |
89 | Damian L. Osisek | US | Vestal, NY | Apr 19, 2018 / 20180107480 - FUNCTION VIRTUALIZATION FACILITY FOR FUNCTION QUERY OF A PROCESSOR | 14 |
90 | Bruce C. Giamei | US | Poughkeepsie, NY | Dec 19, 2013 / 20130339666 - SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION | 14 |
91 | Robert Valentine | IL | Qiryat Tivon | Oct 13, 2016 / 20160299763 - Methods, Apparatus, Instructions and Logic to Provide Permute Controls With Leading Zero Count Functionality | 14 |
92 | John Moussouris | US | Palo Alto, CA | Jul 04, 2013 / 20130173888 - Processor for Executing Wide Operand Operations Using a Control Register and a Results Register | 14 |
93 | Toshio Yoshida | JP | Kawasaki | Sep 27, 2012 / 20120246409 - ARITHMETIC PROCESSING UNIT AND ARITHMETIC PROCESSING METHOD | 14 |
94 | Ravi Rajwar | US | Portland, OR | Dec 29, 2016 / 20160378490 - PROTECTING CONFIDENTIAL DATA WITH TRANSACTIONAL PROCESSING IN EXECUTE-ONLY MEMORY | 14 |
95 | Brent Bean | US | Austin, TX | Apr 14, 2016 / 20160105282 - KEY EXPANSION LOGIC USING DECRYPTION KEY PRIMITIVES | 14 |
96 | Suleyman Sair | US | Chandler, AZ | Jun 22, 2017 / 20170177356 - Systems, Apparatuses, and Method for Strided Access | 14 |
97 | Bruce M. Fleischer | US | Bedford Hills, NY | Jun 25, 2015 / 20150177811 - POWER MANAGEMENT FOR IN-MEMORY COMPUTER SYSTEMS | 14 |
98 | Erich James Plondke | US | Austin, TX | Feb 16, 2017 / 20170046156 - TABLE LOOKUP USING SIMD INSTRUCTIONS | 14 |
99 | Yaakov Yaari | IL | Haifa | Oct 29, 2015 / 20150310332 - Predicting outcome based on input | 14 |
100 | Ravi Nair | US | Briarcliff Manor, NY | Jan 13, 2022 / 20220012741 - FRAUD DETECTION USING MULTI-TASK LEARNING AND/OR DEEP LEARNING | 14 |