Patent application number | Description | Published |
20100246277 | METHOD OF MAINTAINING THE STATE OF SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 09-30-2010 |
20100246284 | SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. | 09-30-2010 |
20100259296 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A configurable integrated circuit (IC) system comprising: a first die comprising input/output cells; and a configurable logic second die connected by a first plurality of through-silicon-vias (TSVs) to the first die. | 10-14-2010 |
20100283504 | METHOD FOR FABRICATION OF A SEMICONDUCTOR ELEMENT AND STRUCTURE THEREOF - Re-programmable antifuses and structures utilizing re-programmable antifuses are presented. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not to conduct by applying second voltage across it, wherein the second voltage is higher than the first voltage. Other embodiments of antifuses include an initializing step prior to programming. | 11-11-2010 |
20100289064 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layers; wherein the second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands wherein each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 11-18-2010 |
20100289524 | Method for Fabrication of a Semiconductor Element and Structure Thereof - Re-programmable antifuses and structures utilizing re-programmable antifuses are presented herein. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not to conduct by applying second voltage across it, wherein the second voltage is higher than the first voltage. Additionally, the re-programmable antifuses may be configured to a permanently conductive state by applying an even higher voltage across it. | 11-18-2010 |
20100291749 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks. | 11-18-2010 |
20100295136 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 11-25-2010 |
20110031997 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the at least one antifuse. | 02-10-2011 |
20110037497 | Method for Fabrication of a Semiconductor Device and Structure - A novel method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the antifuse. | 02-17-2011 |
20110049577 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 03-03-2011 |
20110084314 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 04-14-2011 |
20110092030 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells. | 04-21-2011 |
20110108888 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells. | 05-12-2011 |
20110121366 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device includes a first single crystal silicon layer including first transistors, a first alignment mark, and at least one metal layer overlying the first single crystal silicon layer for interconnecting the first transistors; a second layer overlying the at least one metal layer, wherein the second layer includes a plurality of second transistors; and a connection path connecting the first transistors and the second transistors and including at least a first strip, a second strip, and a through via connecting the first strip and the second strip, wherein the second strip is substantially orthogonal to the first strip and wherein the through via is substantially away from both ends of the first strip and both ends of the second strip. | 05-26-2011 |
20110199116 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die. | 08-18-2011 |
20110225330 | PORTABLE UNIVERSAL COMMUNICATION DEVICE - Embodiments of the invention provide a portable device comprising at least one processor. The portable device also comprises a memory coupled to the processor comprising data. Further, the portable device comprises a detector configured to detect at least one external device. The at least one external device is configured to connect to the portable device. Further, the portable device comprises an interface to connect to the at least one external device. The interface is configured to transmit or receive one or more control signals excluding the data. Furthermore, the portable device comprises a controller configured to enable controlling of the portable device from the at least one external device; and controlling of the at least one external device from the portable device through the interface. | 09-15-2011 |
20110233617 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 09-29-2011 |
20110233676 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 09-29-2011 |
20120012895 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor. | 01-19-2012 |
20120012915 | SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. | 01-19-2012 |
20120014188 | METHOD OF MAINTAINING THE STATE OF SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 01-19-2012 |
20120028436 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks. | 02-02-2012 |
20120032294 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark. | 02-09-2012 |
20120063574 | SYSTEMS AND METHODS FOR VISUAL PRESENTATION AND SELECTION OF IVR MENU - Embodiments of the invention provide a system for enhancing user interaction with Interactive Voice Response (IVR) destinations, the system comprising: a processor; and a memory coupled to the processor, the memory comprising: data encoding a database, the database comprising a list of telephone numbers associated with one or more destinations implementing an IVR; instructions executable by the processor for automatically communicating with at least one user; and instructions executable by the processor to pull at least one menu from the database and display the menu to the at least one user, wherein the menu is associated with a telephone number dialed by the at least one user, and wherein the menu comprises at least one icon. | 03-15-2012 |
20120081940 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type. | 04-05-2012 |
20120081941 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type. | 04-05-2012 |
20120081976 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 04-05-2012 |
20120081977 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 04-05-2012 |
20120086067 | SEMICONDUCTOR DEVICE AND STRUCTURE - A device, comprising: a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline, wherein said first layer comprises first transistors, wherein said second layer comprises second transistors, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said first transistors and said second transistors are processed following the same lithography step. | 04-12-2012 |
20120088355 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: a first monocrystalline layer comprising semiconductor regions, overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer comprising semiconductor regions overlying the isolation layer; and etching portions of the first monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer. | 04-12-2012 |
20120088367 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer. | 04-12-2012 |
20120091474 | NOVEL SEMICONDUCTOR AND OPTOELECTRONIC DEVICES - A light-emitting integrated wafer structure, comprising: three overlying layers, wherein each of the three overlying layers emits light at a different wavelength and wherein at least one of the three overlying layers is transferred to the light-emitting integrated wafer structure using one of atomic species implants assisted cleaving, laser lift-off, etch-back, or chemical-mechanical-polishing (CMP). | 04-19-2012 |
20120094414 | NOVEL SEMICONDUCTOR AND OPTOELECTRONIC DEVICES - A method for fabricating a light-emitting integrated device, comprises overlying three layers, wherein each of the three layers emits light at a different wavelength, and wherein the overlying comprises one of: performing an atomic species implantation, performing a laser lift-off, performing an etch-back, or chemical-mechanical polishing (CMP). | 04-19-2012 |
20120107967 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including first transistors and interconnecting metal layers to perform at least one first electronic function; providing a second monocrystalline layer on top of the metal layers, wherein the second monocrystalline layer includes second transistors to perform at least one second electronic function and substituting the at least one first electronic function with the at least one second electronic function. | 05-03-2012 |
20120129301 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer. | 05-24-2012 |
20120193681 | 3D SEMICONDUCTOR DEVICE - A wafer includes a group of tiles of programmable logic formed thereon, wherein each tile comprises a micro control unit (MCU) communicating with adjacent MCUs, and wherein each MCU is controlled in a predetermined order of priority by adjacent MCUs; and dice lines on the wafer to separate the group into one or more end-devices. | 08-02-2012 |
20120193719 | SEMICONDUCTOR DEVICE AND STRUCTURE - A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors. | 08-02-2012 |
20120193806 | 3D SEMICONDUCTOR DEVICE - A three dimensional semiconductor device includes a first die; and a second die overlaying the first die, wherein said first die comprises signals are selectively coupleable to the second die using Through Silicon Vias. | 08-02-2012 |
20120194216 | 3D Semiconductor Device - A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer. | 08-02-2012 |
20120194218 | 3D Semiconductor Device - A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer. | 08-02-2012 |
20120196390 | 3D SEMICONDUCTOR DEVICE WITH REDUNDANCY - A method for manufacturing system includes 3D-IC comprising at least first layer of first transistors and second layers of second transistors and, perform a test for the circuit constructed with said first transistors and switch in function constructed with said second transistors to replace function constructed with said first transistors. | 08-02-2012 |
20120196409 | 3D SEMICONDUCTOR DEVICE - A semiconductor device includes a first mono-crystallized semiconductor layer; and a second mono-crystallized semiconductor layer; wherein said first and second mono-crystallized semiconductor layers are overlaying one on top of the other, and wherein said first mono-crystallized semiconductor layer comprise repeating memory structure with sub structures defined by etching. | 08-02-2012 |
20120220102 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing semiconductor wafers, the method comprising providing a donor wafer comprising a semiconductor substrate; performing a lithography step and process the said donor wafer accordingly; and performing at least two layers transfer out of said donor wafer wherein each of said at least two layer had been effected by said process | 08-30-2012 |
20120223738 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 09-06-2012 |
20120230123 | Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 09-13-2012 |
20120231572 | METHOD FOR FABRICATING NOVEL SEMICONDUCTOR AND OPTOELECTRONIC DEVICES - A method for fabricating an integrated device, the method including, overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of the first and second crystalline layers has been transferred by performing an atomic species implantation, and wherein at least one of the first and second crystalline layers includes single crystal transistors. | 09-13-2012 |
20120248595 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer. | 10-04-2012 |
20120273955 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor. | 11-01-2012 |
20120306082 | SEMICONDUCTOR DEVICE AND STRUCTURE FOR HEAT REMOVAL - A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion. | 12-06-2012 |
20120313227 | SEMICONDUCTOR DEVICE AND STRUCTURE FOR HEAT REMOVAL - A semiconductor device, including: a semiconductor substrate with first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors. | 12-13-2012 |
20120322203 | METHOD TO CONSTRUCT SYSTEMS - A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die. | 12-20-2012 |
20130015517 | Semiconductor Memory Device Having Electrically Floating Body Transistor, Semiconductor Memory Device Having Both Volatile and Non-Volatile Functionality and Method of Operating - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided. | 01-17-2013 |
20130020707 | NOVEL SEMICONDUCTOR SYSTEM AND DEVICE - A 3D IC based system including: a first semiconductor layer including first alignment marks and first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer; and wherein the second transistors include a plurality of N-type transistors and P-type transistors, and wherein the second mono-crystallized semiconductor layer is transferred from a reusable donor wafer. | 01-24-2013 |
20130021060 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - Two configurable systems including: a first configurable system including a first configurable logic die connected to at least one first configurable Input-Output die, and a second configurable system including a second configurable logic die connected to at least one second configurable Input-Output die; wherein the first configurable logic die includes a multiplicity of device layers, and the second configurable logic die includes a multiplicity of device layers; wherein the first configurable logic die size is substantially larger than the second configurable logic die size, and wherein the device layers of the second configurable logic die are substantially the same as a portion of the corresponding device layers of the first configurable logic die. | 01-24-2013 |
20130022181 | SYSTEMS AND METHODS FOR VISUAL PRESENTATION AND SELECTION OF IVR MENU - Embodiments of the invention provide a system for generating an Interactive Voice Response (IVR) database, the system comprising a processor and a memory coupled to the processor. The memory comprising a list of telephone numbers associated with one or more destinations implementing IVR menus, wherein the one or more destinations are grouped based on a plurality of categories of the IVR menus. Further the memory includes instructions executable by said processor for automatically communicating with the one of more destinations, and receiving at least one customization record from said at least one destination to store in the IVR database. | 01-24-2013 |
20130022183 | SYSTEMS AND METHODS FOR VISUAL PRESENTATION AND SELECTION OF IVR MENU - Embodiments of the invention provide a system for generating an Interactive Voice Response (IVR) database, the system comprising a processor and a memory coupled to the processor. The memory comprising a list of telephone numbers associated with one or more destinations implementing IVR menus, wherein the one or more destinations are grouped based on a plurality of categories of the IVR menus. Further the memory includes instructions executable by said processor for automatically communicating with the one of more destinations, and receiving at least one customization record from said at least one destination to store in the IVR database. | 01-24-2013 |
20130022191 | SYSTEMS AND METHODS FOR VISUAL PRESENTATION AND SELECTION OF IVR MENU - Embodiments of the invention provide a system for generating an Interactive Voice Response (IVR) database, the system comprising a processor and a memory coupled to the processor. The memory comprising a list of telephone numbers associated with one or more destinations implementing IVR menus, wherein the one or more destinations are grouped based on a plurality of categories of the IVR menus. Further the memory includes instructions executable by said processor for automatically communicating with the one of more destinations, and receiving at least one customization record from said at least one destination to store in the IVR database. | 01-24-2013 |
20130069191 | NOVEL SEMICONDUCTOR AND OPTOELECTRONIC DEVICES - An integrated device, the device including a first crystalline layer covered by an oxide layer, a second crystalline layer overlying the oxide layer, wherein the first and second crystalline layers are image sensor layers, and the device includes a third crystalline layer, wherein the third crystalline layer includes single crystal transistors. | 03-21-2013 |
20130080898 | SYSTEMS AND METHODS FOR ELECTRONIC COMMUNICATIONS - Embodiments of the invention provide a system for enhancing user interaction with objects connected to a network. The system includes a processor, a display screen, a memory coupled to the processor. The memory comprises a database including a list of two or more objects and instructions executable by the processor to display a menu. The menu is associated with at least two independent objects. And the two independent objects are produced by two independent vendors. | 03-28-2013 |
20130083589 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors. | 04-04-2013 |
20130119557 | SYSTEMS COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - Two systems including: a first system including a first die connected to a second die; and a second system including a third die connected to a fourth die; wherein the connected includes at least one through silicon via (TSV), and wherein the first die is substantially the same as the third die, and the second die is substantially different than the fourth die. | 05-16-2013 |
20130122672 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented. | 05-16-2013 |
20130193488 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer overlying the at least one metal layer; wherein the second layer includes second transistors, the second transistors include mono-crystal, the second transistors include P type transistors and N type transistors, and the second transistors are aligned to the first alignment mark with less than 40 nm alignment error. | 08-01-2013 |
20130241026 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, wherein the second layer is less than 2 micron thick, wherein the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, wherein the connection path includes at least one through-layer via, and wherein the through-layer via includes material whose co-efficient of thermal expansion is within 50 percent of the second layer coefficient of thermal expansion. | 09-19-2013 |
20130267046 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors. | 10-10-2013 |
20140042503 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 02-13-2014 |
20140059411 | NOVEL COMPUTING SYSTEM - A computing system including a processor, display, pointing device and memory; wherein the memory includes a text file, a graphics file corresponding to said text file and executable instructions to perform at least these actions (i) identify a selection of an alphanumeric identifier within a displayed text file, and then (ii) identify the appearance of the identifier in a corresponding graphics file, and then (iii) display a page of the graphics file comprising the appearance of the identifier. | 02-27-2014 |
20140145272 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region. | 05-29-2014 |
20140156556 | TIME VARIANT RATING SYSTEM AND METHOD THEREOF - Embodiments of the present invention provide a system for enhancing reliability in computation of ratings provided by a user over a social network. The system comprises of a processor and a memory coupled to the processor. The memory further comprises a rater score database, a satisfaction database, a social network registration database, a user profile database, and a plurality of instruction executable by the processor. Said instructions in the memory are enabled to accept a message from at least one user wherein said message comprises a satisfaction score associated with at least one service provider and to retrieve a rater score associated with said at least one user from said rater score database. Further, the memory includes instructions in order to compute a new satisfaction score based on said rater score and said satisfaction score and update said satisfaction database to include said new satisfaction score. In a similar manner, the new satisfaction score can be computed based upon the information stored in the social network registration database and user profile database. | 06-05-2014 |
20140156758 | RELIABLE RATING SYSTEM AND METHOD THEREOF - Embodiments of the invention provide means to the users of the system to provide ratings and corresponding feedback for enhancing the genuineness in the ratings. The system includes a memory coupled to a processor. The memory includes one or more instructions executable by the processor to enable the users of the system to rate each other based on at least one of sharing, exchanging, and selling one of activity, service or product. The system may provide a mechanism to encourage genuineness in ratings provided by the users. Furthermore, the instructions facilitate the rating receivers to provide feedbacks corresponding to the received ratings. The feedback includes accepting or objecting to a particular rating. Moreover, the memory includes instructions executable by the processor to enable the system to determine genuineness of an objection raised by a rating receiver. | 06-05-2014 |
20140160868 | Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell, and accessing the cell. | 06-12-2014 |
20140307501 | SCALABLE FLOATING BODY MEMORY CELL FOR MEMORY COMPILERS AND METHOD OF USING FLOATING BODY MEMORIES WITH MEMORY COMPILERS - A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided. | 10-16-2014 |
20140319621 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 10-30-2014 |
20140340972 | Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 11-20-2014 |
20150010136 | SYSTEMS AND METHODS FOR VISUAL PRESENTATION AND SELECTION OF IVR MENU - Embodiments of the invention provide a system for generating an Interactive Voice Response (IVR) database, the system comprising a processor and a memory coupled to the processor. The memory comprising a list of telephone numbers associated with one or more destinations implementing IVR menus, wherein the one or more destinations are grouped based on a plurality of categories of the IVR menus. Further the memory includes instructions executable by said processor for automatically communicating with the one of more destinations, and receiving at least one customization record from said at least one destination to store in the IVR database. | 01-08-2015 |
20150054090 | 3DIC SYSTEM WITH A TWO STABLE STATE MEMORY - A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region. | 02-26-2015 |
20150061036 | NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; a second set of external connections overlying the second layer to connect the device to external devices; and an interconnection layer in-between the first layer and the second layer, where the interconnection layer includes copper or aluminum. | 03-05-2015 |
20150069523 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive structure underneath at least one of the second single crystal transistors, the at least one conductive structure is constructed to provide a back-bias to at least one of the second single crystal transistors. | 03-12-2015 |