Patent application number | Description | Published |
20120237851 | PERFLUORINATED ION EXCHANGE RESIN, PREPARATION METHOD AND USE THEREOF - The present invention provides a perfluorinated ion exchange resin, whose structural formula is shown in formula M. The present invention also provides preparation method of the perfluorinated ion exchange resin, comprising subjecting tetrafluoroethylene monomers and two kinds of sulfonyl fluoride-containing vinyl ether monomers in the presence of initiator to ternary copolymerization. The perfluorinated ion exchange resin provided in accordance with the present invention can fulfill the requirements of mechanical strength and ion exchange capacity at the same time and has good thermal stability. | 09-20-2012 |
20120282541 | HIGH EXCHANGE CAPACITY PERFLUORINATED ION EXCHANGE RESIN, PREPARATION METHOD AND USE THEREOF - The present invention provides a high exchange capacity perfluorinated resin comprising two kinds of sulfonyl fluoride-containing short pendant groups of different structures, which is prepared by copolymerizing tetrafluoroethylene, vinyl ether monomers comprising two kinds of sulfonyl fluoride-containing short pendant groups of different structures, and vinyl ether monomer comprising bromine-containing pendant group, wherein based on all monomer units in the copolymer, the mol % of tetrafluoroethylene monomer is 50-85%, the mol % of vinyl ether monomers comprising two kinds of sulfonyl fluoride-containing short pendant groups of different structures is 5-49% and the mol % of vinyl ether monomer comprising bromine-containing pendant group is 1-10%. Perfluorinated ion exchanges membrane prepared from such perfluorinated resin have resistance to various chemical media, high ion exchange capacity, high conductivity, high mechanical strength, high size stability, low membrane electrical resistance and long service life, and may be applied in fuel cells or high-temperature fuel cells. | 11-08-2012 |
Patent application number | Description | Published |
20120181508 | Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits - A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer. | 07-19-2012 |
20120223292 | Multilayer-Interconnection First Integration Scheme for Graphene and Carbon Nanotube Transistor Based Integration - Integrated circuit multilayer integration techniques are provided. In one aspect, a method of fabricating an integrated circuit is provided. The method includes the following steps. A substrate is provided. A plurality of interconnect layers are formed on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack. At least one transistor is formed on a top-most layer of the stack. | 09-06-2012 |
20120292702 | Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits - A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer. | 11-22-2012 |
Patent application number | Description | Published |
20150221712 | TILED OLED DISPLAY AND MANUFACTURING METHOD THEREOF - The present invention is applicable to the field of display technologies and provides a tiled OLED display, and the tiled OLED display includes an OLED front panel and a single-structure TFT driving backplane, where a protection substrate is disposed on a light-emitting side of the OLED front panel; the OLED front panel includes multiple OLED front panel units that are tiled to each other; and the OLED front panel unit is joined to the TFT driving backplane by using conductive film. In the present invention, by tiling the OLED front panel on the TFT backplane, production efficiency and a yield rate of the display are improved, thereby reducing a cost. By tiling the OLED front panel, a tiling gap is narrowed, thereby implementing seamless tiling. Compared with a traditional structure that uses an optical lens to eliminate a tiling gap, the yield rate of the tiled display is improved. By joining the OLED front panel to the TFT driving backplane by using the conductive film, a display aperture ratio is improved, and a problem that it is difficult to control alignment precision and stability is poor is overcome. | 08-06-2015 |
20150270290 | METAL OXIDE TFT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a metal oxide TFT device is provided. The method includes: selecting a substrate and forming a gate electrode on a first side of the substrate; sequentially depositing an insulating layer, a semiconductor layer, and a photoresist layer on the gate electrode; using the gate electrode as a photomask, exposing from a second side of the substrate and reserving the photoresist layer aligning to the gate electrode; depositing an electrode layer on the semiconductor layer and the reserved photoresist layer; stripping the reserved photoresist layer and lifting off the electrode layer stacked on the reserved photoresist layer; etching a part of the reserved electrode layer and the semiconductor layer, and forming a source electrode, a drain electrode, and a semiconductor island. The method realizes a self-alignment using the gate electrode as the photomask when forming the source, drain electrodes and the channel. Therefore, the manufacturing processes become simple and more accurate. | 09-24-2015 |
20150295015 | DOUBLE-SIDED DISPLAY AND METHOD OF MANUFACTURING SAME - A double-sided display and a method of manufacturing the double-side display are provided. The double-sided display includes a substrate having a plurality of holes penetrating through the substrate, a TFT driving circuit, a front-side light-emitting structure, a back-side light-emitting structure, and a plurality of driving electrodes. The front-side and the back-side light-emitting structures are respectively disposed on two opposite sides of the substrate. The TFT driving circuit is disposed on one of the two opposite sides, and the driving electrodes are disposed on the other one of the two opposite sides. The TFT driving circuit is configured to drive one of the front-side and back-side light-emitting structures to display images, and is further configured to drive the other one of the front-side and back-side light-emitting structures to display images in cooperation with the driving electrodes connected to the TFT driving circuit via the holes. | 10-15-2015 |
20150295016 | DOUBLE-SIDED DISPLAY AND CONTROL METHOD THEREOF - A double-sided display and a method for controlling the same are provided. The double-sided display includes a plurality of pixel units and a plurality of circuits. The pixel units are disposed on each of a front side and a back side of the double-sided display, and the pixel units on the front side are opposite to the pixel units on the back side in a one-to-one manner. A pixel unit on the front side and a pixel unit on the back side opposite to the pixel unit on the front side are controlled by an identical circuit. Each of the circuits includes a switching transistor. The switching transistor includes a first input terminal connected to a scan line, a second input terminal connected to a data line, and an output terminal connected to the opposite pixel units on the front side and the back side. | 10-15-2015 |
20150303308 | SELF-ALIGNED METAL OXIDE THIN-FILM TRANSISTOR COMPONENT AND MANUFACTURING METHOD THEREOF - The present invention is applicable to the field of electronic component technologies and provides a manufacturing method of a self-aligned metal oxide TFT component, including: selecting a substrate and preparing a gate on the substrate; successively disposing an insulation layer, a transparent electrode layer, and a photoresist on the gate; using the gate as a mask to perform exposure from a back side of the substrate, so as to form a source and a drain that are aligned with the gate; depositing a metal oxide semiconductor layer on the transparent electrode layer; performing etching on the semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of the metal oxide semiconductor layer; and depositing a passivation layer and leading out the source and the drain. In the present invention, a transparent conductor is used as the electrode layer, and a bottom gate is used as a mask to perform back exposure, so as to perform etching on the source and the drain, thereby implementing a self-alignment between the source or the drain and the gate, effectively reducing parasitic capacitance, and improving component performance. The component is of a bottom-gate bottom-contact structure, and there is no need to manufacture an etch-stop layer, thereby simplifying a process, reducing use of a photolithographic mask, improving production efficiency, and improving an electrical property of the component. | 10-22-2015 |
20150349098 | A MANUFACTURING METHOD OF A THIN FILM TRANSISTOR AND PIXEL UNIT THEREOF - The present invention provides a method of manufacturing a thin film transistor and a pixel unit thereof, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate; through the same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate, while retaining: the metal oxide layer, the gate insulating layer, the gate metal layer and the etching barrier layer in a gate region, and the part of the metal oxide layer, the gate insulating layer and the gate metal layer in source and drain regions for forming contact vias; and exposing the remaining metal oxide layer in the source region and in the drain region; depositing a passivation layer, etching and metallizing the exposed oxide in the source and drain regions to form the source and drain contact vias. | 12-03-2015 |
20150382474 | METHOD FOR FABRICATING FLEXIBLE ELECTRONIC DEVICE AND SUBSTRATE FOR FABRICATING THE SAME - The present invention relates to the field of electronic device fabrication, provides a method for fabricating a flexible electronic device, and is intended to address the problems present in the prior art that the adhesive cannot be completely peeled off and the flexible substrate is damaged during peeling the flexible substrate from the rigid substrate in the flexible electronic device fabrication. The fabrication method comprises providing a channel on a rigid substrate; adhering a flexible substrate to the rigid substrate with an adhesive; fabricating an electronic device on the flexible substrate; injecting a chemical substance into the channel; and reacting the chemical substance with the adhesive, and peeling the flexible substrate from the rigid substrate. The present invention also provides a substrate for fabricating a flexible electronic device. In the present invention, a channel is provided on the rigid substrate to enhance the efficiency and speed of the reaction between the chemical substance with the adhesive, so that the flexible substrate can be completely and automatically peeled from the rigid substrate rapidly, and the chemical substance which reacts with the adhesive will not cause a damage to the flexible substrate or the electronic device. | 12-31-2015 |
20160049500 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND PIXEL UNIT THEREOF - The present invention is suitable to the field of electronic technology, and provides a method of manufacturing a thin film transistor and a pixel unit thereof, wherein when the thin film transistor is manufactured, the gate metal layer is used as a mask, and exposed from the back of the substrate to position the channel and the source and drain of the thin film transistor, so that the channel is self-aligned with the gate, and the source and drain are self-aligned with the gate and are symmetrical, and the thin film transistor thus manufactured has a small parasitic capacitance, and the circuit manufactured therewith is fast in operation, and less prone to occurring short circuit or open circuit. In the present invention, the characteristics that the channel is self-aligned with the gate, and the source and drain are self-aligned with the gate and are symmetrical avoid the alignment precision requirement on the mask plate in the production, thus reducing the need for the high precision lithographic apparatus, and reducing the costs and increasing the yield. In addition, the present process is suitable for manufacturing a pixel unit of a thin film transistor, the manufacturing process only requires four mask sets which do not require the critical alignment. As compared with other four mask processes which use the gray tone masks, the present process can increase the yield and reduce the costs. | 02-18-2016 |
20160056217 | SUBSTRATE-LESS FLEXIBLE DISPLAY AND METHOD OF MANUFACTURING THE SAME - A substrate-less display device is disclosed. The substrate-less display device includes a barrier stack. The barrier stack includes a plurality of inorganic barrier films and a plurality of polymer films. The inorganic barrier films and the polymer films are alternatively disposed. The substrate-less display device further includes a thin-film-transistor (TFT) device layer disposed on the barrier stack, a display medium layer disposed on the TFT device layer, and an encapsulation layer disposed on the display medium layer. | 02-25-2016 |