Patent application number | Description | Published |
20100174955 | TEST AND BRING-UP OF AN ENHANCED CASCADE INTERCONNECT MEMORY SYSTEM - A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features. | 07-08-2010 |
20120303855 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE ACCELERATORS OFFLOADING FIRMWARE FOR BUFFER ALLOCATION AND AUTOMATICALLY DMA - A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations. | 11-29-2012 |
20120303859 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH PARITY UPDATE FOOTPRINT MIRRORING - A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations. | 11-29-2012 |
20120303883 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CACHE DATA/DIRECTORY MIRRORING - A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode. | 11-29-2012 |
20120303886 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE CHAINS TO SELECT PERFORMANCE PATH - A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance. | 11-29-2012 |
20120303909 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED HARDWARE AND SOFTWARE INTERFACE - A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor. | 11-29-2012 |
20120303922 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED RESOURCE POOL ALLOCATION - A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance. | 11-29-2012 |
20120304001 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS AND ERROR RECOVERY FIRMWARE PATH - A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations. | 11-29-2012 |
20120304198 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS MINIMIZING HARDWARE/FIRMWARE INTERACTIONS - A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor. | 11-29-2012 |
Patent application number | Description | Published |
20120200908 | ELECTROCHROMIC MULTI-LAYER DEVICES WITH SPATIALLY COORDINATED SWITCHING - A multi-layer device comprising a first substrate and a first electrically conductive layer on a surface thereof, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position. | 08-09-2012 |
20140043667 | ELECTROCHROMIC MULTI-LAYER DEVICES WITH COMPOSITE ELECTRICALLY CONDUCTIVE LAYERS - A multi-layer device comprising a first substrate and a first electrically conductive layer on a surface thereof, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position. | 02-13-2014 |
20140043668 | ELECTROCHROMIC MULTI-LAYER DEVICES WITH CURRENT MODULATING STRUCTURE - A multi-layer device comprising a first substrate, a first electrically conductive layer on a surface thereof, and a first current modulating layer, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position. | 02-13-2014 |
20140043669 | ELECTROCHROMIC MULTI-LAYER DEVICES WITH COMPOSITE CURRENT MODULATING STRUCTURE - A multi-layer device comprising a first substrate, a first electrically conductive layer and a first current modulating structure on a surface thereof, the first current modulating structure comprising a composite of a resistive material and a patterned insulating material, the first current modulating structure having a cross-layer resistance to the flow of electrical current through the first current modulating structure that varies as a function of position. | 02-13-2014 |
20140204448 | ELECTROCHROMIC MULTI-LAYER DEVICES WITH SPATIALLY COORDINATED SWITCHING - A multi-layer device comprising a first substrate and a first electrically conductive layer on a surface thereof, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position. | 07-24-2014 |
Patent application number | Description | Published |
20090101870 | ELECTRON TRANSPORT BI-LAYERS AND DEVICES MADE WITH SUCH BI-LAYERS - There are disclosed bi-layer compositions which are useful as electron transport layers. The bi-layers have a first layer containing electron transport material and a second layer containing a fullerene. Also disclosed are organic light emitting diodes including the electron transport bi-layers. | 04-23-2009 |
20110017980 | PROCESS AND MATERIALS FOR MAKING CONTAINED LAYERS AND DEVICES MADE WITH SAME - There is provided a process for forming a contained second layer over a first layer, including the steps:
| 01-27-2011 |
20110095308 | PROCESS FOR FORMING AN ELECTROACTIVE LAYER - There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes the steps of providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of −25 to 80° C. and under a vacuum in the range of 10 | 04-28-2011 |
20130299800 | PROCESS FOR FORMING AN ELECTROACTIVE LAYER - There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes the steps of providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of −25 to 80° C. and under a vacuum in the range of 10 | 11-14-2013 |
20140034941 | PROCESS AND MATERIALS FOR MAKING CONTAINED LAYERS AND DEVICES MADE WITH SAME - There is provided a process for forming a contained second layer over a first layer, including the steps:
| 02-06-2014 |
Patent application number | Description | Published |
20140021097 | SILICA SOL BOUND CATALYTIC CRACKING CATALYST STABILIZED WITH MAGNESIUM - A rare earth free particulate catalytic cracking catalyst which comprises a zeolite having catalytic cracking ability under catalytic cracking conditions, an acidified silica sol binder, magnesium salt, clay and a matrix material. The catalytic cracking catalyst has a high matrix surface area and is useful in a catalytic cracking process, in particularly, a fluid catalytic cracking process, to provide increased catalytic activity and improved hydrogen and coke selectivity without the need to incorporate rare earth metals. | 01-23-2014 |
20140021098 | HIGH MATRIX SURFACE AREA CATALYTIC CRACKING CATALYST STABILIZED WITH MAGNESIUM AND SILICA - Particulate catalytic cracking catalysts which comprise a zeolite having catalytic cracking ability under catalytic cracking conditions, added silica, a magnesium salt, an alumina containing binder, clay and optionally, a matrix material. The catalytic cracking catalyst has a high matrix surface area and is useful in a catalytic cracking process, in particularly, a fluid catalytic cracking process, to provide increased catalytic activity and improved coke and hydrogen selectivity without the need to incorporate rare earth metals. | 01-23-2014 |