Ziaja
Hermann Ziaja, Burgthann DE
Patent application number | Description | Published |
---|---|---|
20100181446 | CONNECTION DEVICE - A connection device for adjustably connecting a surgical apparatus connected to a first end of the connection device to an attachment part on a stationary device, such as an operating table, which can be connected to a second end of the connection device. The connection device has a first holding arm and a second holding arm, connected to the first holding arm in a hinged fashion via a ball and socket joint. A clamping apparatus is provided for detachably clamping the ball of the ball and socket joint in the ball and socket joint receptacle. A hydraulic apparatus is also provided which, when operated, loads the clamping apparatus with a force opposing the clamping force. Further, a clamping force transformation apparatus transforms the force applied by the clamping apparatus into a larger clamping force. | 07-22-2010 |
Jason Ziaja, Cedar Park, TX US
Patent application number | Description | Published |
---|---|---|
20160132652 | COMMUNICABLE DISEASE TRACKING - Systems and methods for controlling the spread of a communicable disease are provided. A combination of physiological data and location data is used to estimate the likelihood that an individual is ill. Once an individual is determined to be ill, the individual's location history may be examined and individuals who were exposed to the individual identified. By tracking individuals who may be ill or who have reported themselves to be ill, and by identifying individuals with a possible exposure to those who may be ill, potential carriers of illness can be quarantined and their access to areas where communicable diseases pose a high risk limited. | 05-12-2016 |
Thomas A. Ziaja, Austin, TX US
Patent application number | Description | Published |
---|---|---|
20100037111 | METHOD AND APPARATUS FOR TESTING DELAY FAULTS - An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device with the high-speed processor during testing. Implementations may gate the input clock signal at the clock input to each domain of the SOC processor device rather than at the output of the PLL clock. The gating of the clock signal to each domain may then be controlled by clock stop signals generated by the testing device and sent to the individual domains of the processor device. Gating the clock signal at the domain may provide a more natural state for the circuit during testing as well as allow the test control unit to test the different domains of the SOC device individually. | 02-11-2010 |
20100332924 | AT-SPEED SCAN TESTING OF MEMORY ARRAYS - An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto. | 12-30-2010 |
20150325314 | At-Speed Test of Memory Arrays Using Scan - A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC. | 11-12-2015 |
Thomas Alan Ziaja, Austin, TX US
Patent application number | Description | Published |
---|---|---|
20090013224 | INTEGRATED CIRCUIT WITH BLOCKING PIN TO COORDINATE ENTRY INTO TEST MODE - An integrated circuit (IC) including a blocking pin. An IC may include state logic, a test control unit configured to coordinate access by external circuitry to operating state of the state logic during a test mode, and interface pins configured to couple the integrated circuit to the external circuitry. Shared interface pins may provide input signals to the test control unit during the test mode of operation and may perform distinct I/O functions during normal mode operation. A blocking interface pin, when asserted by external circuitry during normal mode operation, may force test signals derived from at least a portion of the shared interface pins by the test control unit into respective quiescent states, such that subsequent to assertion of the blocking pin, the integrated circuit is operable to enter the test mode of operation from the normal mode of operation without resetting operating state of the state logic. | 01-08-2009 |
20100235683 | TESTING MULTI-CORE PROCESSORS - Methods and apparatuses are disclosed for testing multicore processors. In some embodiments, the tested multicore processor may include at least a first core and a second core, a data input coupled to a first scan chain in the first core and a second scan chain in the second core, and a multiplexer including at least a first input and a second input, the first input coupled with a data output of the first scan chain and the second input coupled with a data output of the second scan chain, the multiplexer further including an output that couples to one or more pins on a package of the processor, the multiplexer further including a select signal that couples to the one or more pins on the package of the processor, and wherein the data input couples to the one or more pins on the package of the processor. | 09-16-2010 |
Timothy Ziaja, Saint Paul, MN US
Patent application number | Description | Published |
---|---|---|
20150217081 | SYSTEM AND METHOD TO OPTIMIZE SLEEP CONDITIONS - A system and related method to optimize the process of getting a child to fall asleep. The system is a computer-implemented system comprising a set of functions or algorithms to assist a child develop a routine to fall asleep. The particular routines are dependent on the age of the child, with three categories being toddlers, preschoolers and school-age children. The routines include providing for the generation of a set of sounds for selectable periods of time, dependent on the age group. The sounds include lullabies, stories, songs and white noise. The time periods range from 15-45 minutes. The method involving the use of the sound generation routine establishes a regularity of process that comforts a child and enhances the likelihood of a good transition to sleep. | 08-06-2015 |