Patent application number | Description | Published |
20100207729 | METHOD AND SYSTEM FOR TESTING RFID TAGS - The present invention provides a method and a system for testing RFID tags, which utilizes a way of adjusting the distance between the RFID tags and interrogator or adjusting the power of the interrogator accompanied with a shielding procedure for testing and classifying the RFID tags. By means of the method and the system of the present invention, it is capable of judging the efficacy and good and bad of the RFID tags, while the interrogatable distance of the RFID tags is capable of being tested effectively. | 08-19-2010 |
20110151121 | CHEMICAL VAPOR DEPOSITION APPARATUS AND METHOD FOR FORMING PARYLENE FILM - A chemical vapor deposition apparatus and a method for forming a parylene film are provided. The chemical vapor deposition apparatus includes a buffer chamber, a deposition chamber, a pyrolysis chamber and an evaporator. The buffer chamber has a first valve and a second valve. The evaporator is connected with the second valve. The pyrolysis chamber is connected with the evaporator through a first pipe, wherein the first pipe has a third valve. The deposition chamber is connected with the pyrolysis chamber. | 06-23-2011 |
20130186514 | Device and method for powder distribution and additive manufacturing method using the same - The present disclosure provides a device and method for powder distribution and an additive manufacturing method, wherein different size or kind of powders could be chosen to be accommodated within a receptacle. The receptacle can uniformly mix the powder by a rotation movement, pour out the powders by the rotation movement and distribute the powders for forming a layer by a translation movement. In another embodiment, the receptacle further comprises a heating element for preheating the powders. Not only can the present disclosure uniformly mix the powders so as to reduce the thermal deformation and distribute the powder layer compactly, but also can the present disclosure distribute different kinds of powder in different layer so as to increase the diversity in additive manufacturing. | 07-25-2013 |
20150174822 | APPARATUS AND METHOD FOR ADJUSTING AND CONTROLLING THE STACKING-UP LAYER MANUFACTURING - An apparatus of adjusting and controlling the stacking-up layer manufacturing comprises a target, a powder providing unit, an energy generating unit, and a magnetism unit. The powder providing unit is coupled on a top of the target. The energy generating unit is also coupled on the top of the target. The powder providing unit provides a powder to a surface of the target. The energy generating unit provides the energy beam to selectively heat the powder on the surface of the target to form a melted or sintered powder layer. The magnetism unit provides a magnetic field to control the solidification of the melted or sintered powder layer. | 06-25-2015 |
Patent application number | Description | Published |
20130087932 | INTEGRATED CIRCUITS AND METHODS OF DESIGNING THE SAME - A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell. | 04-11-2013 |
20130113520 | METHOD AND APPARATUS FOR IMPROVED MULTIPLEXING USING TRI-STATE INVERTER - A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively. | 05-09-2013 |
20130146981 | ANTENNA CELL DESIGN TO PREVENT PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS - An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at V | 06-13-2013 |
20140001595 | Layout Architecture for Performance Improvement | 01-02-2014 |
20140077270 | INTEGRATED CIRCUIT - An integrated circuit includes a first standard cell over a substrate, a power rail, and a first connection plug. The first standard cell includes an active area, at least one gate electrode overlapping the active area of the first standard cell, and at least one metallic line structure overlapping the active area of the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. The power rail is substantially orthogonal to the at least one metallic line structure of the first standard cell. The power rail overlaps the at least one metallic line structure of the first standard cell, and the power rail has a flat edge extending through the first standard cell. The first connection plug is at a region where the power rail overlaps the at least one metallic line structure of the first standard cell. | 03-20-2014 |
20140183647 | INTEGRATED CIRCUIT LAYOUT DESIGN - An integrated circuit layout that includes a first standard cell having a first transistor region and a second transistor region; a second standard cell having a third transistor region and a fourth transistor region. The first and second standard cells adjoin each other at side boundaries thereof and the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous region. | 07-03-2014 |
20140298284 | STANDARD CELL DESIGN LAYOUT - Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant. | 10-02-2014 |
20140327050 | STANDARD CELL HAVING CELL HEIGHT BEING NON-INTEGRAL MULTIPLE OF NOMINAL MINIMUM PITCH - An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch. | 11-06-2014 |
20140327081 | STANDARD CELL METAL STRUCTURE DIRECTLY OVER POLYSILICON STRUCTURE - A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure. | 11-06-2014 |
20140327471 | STANDARD CELLS FOR PREDETERMINED FUNCTION HAVING DIFFERENT TYPES OF LAYOUT - An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch. | 11-06-2014 |
20150031194 | METHOD FOR DESIGNING ANTENNA CELL THAT PREVENTS PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS - An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at V | 01-29-2015 |
20150035070 | METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT - An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor. | 02-05-2015 |
20150067616 | CELL LAYOUT DESIGN AND METHOD - A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell. | 03-05-2015 |
20150149976 | LAYOUT OF AN INTEGRATED CIRCUIT - A cell layout includes a first metal line for VDD power, which includes a first jog coupling to and being perpendicular to the first metal line. A second metal line is for VSS power, and includes a second jog coupling to and being perpendicular to the second metal line. The cell layout includes an upper cell boundary, a lower cell boundary, a first cell boundary and a second cell boundary. The upper cell boundary and the lower cell boundary extend along X direction. The first cell boundary and the second cell boundary extend along Y direction. The upper cell boundary is defined in a portion of the first metal line. The lower cell boundary is defined in a portion of the second metal line. The first cell boundary is defined in a portion of the first jog and a portion of the second jog. | 05-28-2015 |
20150347659 | SYSTEM AND METHOD OF LAYOUT DESIGN FOR INTEGRATED CIRCUITS - A system and method of layout design for an integrated circuit and integrated circuit, the method includes positioning all conductive traces of a first mask pattern, in a first direction, wherein the conductive traces of the first mask pattern are in a first conductive layer. The method also includes positioning all conductive traces of a second mask pattern, in the first direction, wherein the conductive traces of the second mask pattern are in the first conductive layer, and the second mask pattern is offset from the first mask pattern in a second direction different from the first direction. | 12-03-2015 |
20150356225 | MASKS FORMED BASED ON INTEGRATED CIRCUIT LAYOUT DESIGN HAVING CELL THAT INCLUDES EXTENDED ACTIVE REGION - A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout. | 12-10-2015 |
Patent application number | Description | Published |
20080215545 | Data file management and search method and system based on file attributes - A data file management and search method based on file attributes is disclosed. At least one data file, externally imported or generated by a user, is retrieved. Attributes of the data file are edited, a virtual catalog corresponding to the data file is generated, and a catalog tree is built according to the data file and the virtual catalog. The virtual catalog and the data file are displayed by a user interface. A search operation is performed based on a search command to locate at least one required virtual catalog or data file among multiple data files and virtual catalogs. A basic operation is implemented on the located virtual catalog or data file. | 09-04-2008 |
20090150332 | VIRTUAL FILE MANAGING SYSTEM AND METHOD FOR BUILDING SYSTEM CONFIGURATION AND ACCESSING FILE THEREOF - A virtual file managing system including a file request managing unit, an information repository, a file namespace managing unit, and a file access managing unit is provided. The file request managing unit receives a file access request issued by a client, and returns a processing result of the file access request. The information repository stores a data structure of the virtual file managing system. The file namespace managing unit looks up address and path content of the file from the information repository according to the file access request. The file access managing unit performs an operation of accessing a file according to the address and path content of the file. | 06-11-2009 |
20090287652 | DISTRIBUTED AUDIO VISUAL SYSTEM AND CONTENT DIRECTORY MANAGEMENT SYSTEM AND METHOD THEREOF - A distributed audio visual (AV) system including a plurality of media servers, a media renderer, and a control point which are connected to each other via a peer-to-peer network is provided. Each of the media servers includes a content directory management unit (CDMU) and a query content information (QCI) module, wherein the CDMU includes a synchronizer module and a content information maintainer (CIM) module. The synchronizer module synchronizes content information of AV contents stored in all the media servers. The CIM module records the content information and establishes an integrated content directory list according to the content information. The QCI module queries the content information. The control point obtains the integrated content directory list from one of the media servers and queries the content information related to all the AV contents, so as to control the media renderer to play the AV contents. | 11-19-2009 |
20120005165 | DATA BACKUP, RECOVERY AND DELETION METHOD THROUGH A DISTRIBUTED NETWORK AND SYSTEM THEREOF - Distributed network-based data backup, recovery and deletion methods and a distributed network system thereof are provided. The methods include respectively establishing peer-to-peer connections between a host storage server and a plurality of peer storage servers, dividing original data into a plurality of data segments, generating a plurality of data segment copies corresponding to the data segments according to a minimum survival rate and the number of peer storage servers. The methods also include transmitting the data segment copies to the peer storage servers, wherein the number of data segment copies for each of the data segments is equal to a redundancy, and the redundancy is smaller than the number of the peer storage servers, and the data segment copies distributed to any one of the peer storage servers correspond to a portion of all the data segments. Accordingly, the methods can effectively and safely backup the original data. | 01-05-2012 |