Patent application number | Description | Published |
20090221501 | MIXING AND MATCHING TC PROTEINS FOR PEST CONTROL - The subject invention relates to the surprising discovery that toxin complex (TC) proteins, obtainable from | 09-03-2009 |
20090318299 | DEVELOPMENT AND USE OF FLUORESCENT PROBES OF UNBOUND ANALYTES - A method for high throughput screening of probes is described. These probes are useful for characterization and measurement of unbound metabolites in a fluid sample, particularly characterization and measurement of levels of unbound free fatty acids. By practice of the disclosed invention, a profile of unbound metabolites can be determined for an individual which can be used to determine the individual's relative risk for disease such as stroke, cardiac disease and cancer. | 12-24-2009 |
20100062948 | USE OF PROBES FOR UNBOUND METABOLITES - Methods of determining levels of unbound metabolites are disclosed. Probes derived from fatty acid binding protein muteins are described that bind preferentially to a number of unbound metabolites including oleate, stearate, linoleate, palmitate, arachidonate and unconjugated bilirubin. A profile for a patient is determined using one or more of the described probes. The profile is useful in diagnosis of disease, particularly myocardial infarction, non-alcoholic fatty liver disease (NAFLD), diabetes, stroke, sepsis and neonatal jaundice. The responses of multiple probes to a test sample are used to classify the degree of acute coronary syndrome by comparison to multi-probe profiles generated from unstable angina, non ST elevation myocardial infarction, and ST elevation myocardial infarction. | 03-11-2010 |
20100298162 | DEVELOPMENT AND USE OF CYSTEINE-LABELED FLUORESCENT PROBES OF UNBOUND ANALYTES - A method for high throughput discovery of proteins fluorescently labeled at a cysteine residue and that undergo a change in fluorescence ratio at 2 wavelengths upon binding an unbound analyte is described. Probes are disclosed which are labeled at a cysteine residue and also probes labeled at both cysteine and lysine with two different fluorophores. These probes are useful for characterization and measurement of hydrophobic species in a fluid sample, particularly characterization and measurement of levels of unbound free fatty acids. A profile of unbound free fatty acids can be determined for an individual which can be used to determine the individual's relative risk for disease. | 11-25-2010 |
20150044692 | DEVELOPMENT AND USE OF FLUORESCENT PROBES OF UNBOUND BILIRUBIN - Identification and use of proteins fluorescently labeled and that undergo a change in fluorescence index upon binding bilirubin are described. Probes are disclosed which are labeled at a cysteine or lysine residue and also probes labeled at both cysteine and lysine with two different fluorophores. These probes are useful for determination of unbound bilirubin levels in a fluid sample. | 02-12-2015 |
Patent application number | Description | Published |
20120309337 | MULTI-LAYER TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTOR (ADC) - A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules. | 12-06-2012 |
20140105339 | SIGNAL RECEIVER WITH MULTI-LEVEL SAMPLING - A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry. | 04-17-2014 |
20150048959 | LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS) - Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC. | 02-19-2015 |
20150048960 | DYNAMIC POWER SWITCHING IN CURRENT-STEERING DACS - Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit. | 02-19-2015 |
20150092899 | SIGNAL RECEIVER WITH MULTI-LEVEL SAMPLING - A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal. | 04-02-2015 |
20150349792 | LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS) - Methods and systems are provided for controlling operations of digital-to-analog converters (DACs), particularly ones comprising multiple DAC elements. In particular, a plurality of DAC elements in a digital-to-analog converter (DAC) may be controlled during digital-to-analog conversions, with the controlling comprising use of a switching arrangement that comprises one or more switching elements configured for controlling switching of each of the plurality of DAC elements. The controlling may comprise forcing one or more of the plurality of DAC elements in the DAC to not switch during the digital-to-analog conversions. Further, the remaining DAC elements may be scrambled. The controlling of the plurality of DAC elements in the DAC may be based on analysis of an input to the DAC that is being converted. The analysis may comprise determining when the input is backed off from full-scale. A switching sequence may be applied, via each of the one or more switching elements. | 12-03-2015 |
Patent application number | Description | Published |
20130320494 | METAL FINGER CAPACITORS WITH HYBRID METAL FINGER ORIENTATIONS IN STACK WITH UNIDIRECTIONAL METAL LAYERS - A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction. | 12-05-2013 |
20140001568 | INTEGRATED CIRCUIT DEVICE FEATURING AN ANTIFUSE AND METHOD OF MAKING SAME | 01-02-2014 |
20140070364 | ANTI-FUSE DEVICE - An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate. | 03-13-2014 |
20140092523 | BONE FRAME, LOW RESISTANCE VIA COUPLED METAL OXIDE-METAL (MOM) ORTHOGONAL FINGER CAPACITOR - An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame. | 04-03-2014 |
20140197519 | MIM CAPACITOR AND MIM CAPACITOR FABRICATION FOR SEMICONDUCTOR DEVICES - In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique. | 07-17-2014 |
20140197520 | RESISTOR AND RESISTOR FABRICATION FOR SEMICONDUCTOR DEVICES - In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor. | 07-17-2014 |
20140203404 | SPIRAL METAL-ON-METAL (SMOM) CAPACITORS, AND RELATED SYSTEMS AND METHODS - Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability. | 07-24-2014 |
20140231957 | COMPLEMENTARY BACK END OF LINE (BEOL) CAPACITOR - A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s). | 08-21-2014 |
20140264629 | LOCAL INTERCONNECT STRUCTURES FOR HIGH DENSITY - A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect. | 09-18-2014 |
20140312500 | COMBINING CUT MASK LITHOGRAPHY AND CONVENTIONAL LITHOGRAPHY TO ACHIEVE SUB-THRESHOLD PATTERN FEATURES - Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion. | 10-23-2014 |
20150028452 | COMPLEMENTARY BACK END OF LINE (BEOL) CAPACITOR - A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s). | 01-29-2015 |
Patent application number | Description | Published |
20140210043 | INTEGRATED CIRCUIT DEVICE FEATURING AN ANTIFUSE AND METHOD OF MAKING SAME - One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage V | 07-31-2014 |
20150076704 | REVERSE SELF ALIGNED DOUBLE PATTERNING PROCESS FOR BACK END OF LINE FABRICATION OF A SEMICONDUCTOR DEVICE - In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench. | 03-19-2015 |
20150091060 | SEMICONDUCTOR DEVICE HAVING HIGH MOBILITY CHANNEL - In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel | 04-02-2015 |
20150235948 | GROUNDING DUMMY GATE IN SCALED LAYOUT DESIGN - A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate. | 08-20-2015 |
20150249038 | SELECTIVE CONDUCTIVE BARRIER LAYER FORMATION - A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer. | 09-03-2015 |
20150255571 | SEMICONDUCTOR DEVICE HAVING A GAP DEFINED THEREIN - In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap. | 09-10-2015 |
20150262875 | SYSTEMS AND METHODS OF FORMING A REDUCED CAPACITANCE DEVICE - A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance. | 09-17-2015 |
20150270134 | METHODS OF FORMING A METAL-INSULATOR-SEMICONDUCTOR (MIS) STRUCTURE AND A DUAL CONTACT DEVICE - A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer. | 09-24-2015 |
20150301973 | VARIABLE INTERCONNECT PITCH FOR IMPROVED PERFORMANCE - A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch. | 10-22-2015 |
20150303145 | BACK END OF LINE (BEOL) LOCAL OPTIMIZATION TO IMPROVE PRODUCT PERFORMANCE - The disclosure relates to a locally optimized integrated circuit (IC) including a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width, and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the IC, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. A method of locally optimizing an IC includes forming the one or more metal interconnects and/or the one or more vias in the first portion of the IC, and forming the one or more metal interconnects and/or the one or the more vias in the second portion of the integrated circuit. | 10-22-2015 |
20150325515 | VIA MATERIAL SELECTION AND PROCESSING - Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material. | 11-12-2015 |
20160027726 | SEMICONDUCTOR DEVICE HAVING AN AIRGAP DEFINED AT LEAST PARTIALLY BY A PROTECTIVE STRUCTURE - An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer. | 01-28-2016 |
20160049487 | DEVICE INCLUDING CAVITY AND SELF-ALIGNED CONTACT AND METHOD OF FABRICATING THE SAME - A device includes a first structure and a second structure. The second structure is separated from the first structure by a cavity. The device further includes a seal material, an etch stop material defining an etched region, and a self-aligned contact (SAC). The seal material is configured to seal the cavity, and the SAC is formed within the etched region. The SAC adjoins the seal material, the etch stop material, or a combination thereof. | 02-18-2016 |
20160071795 | CAPACITOR FROM SECOND LEVEL MIDDLE-OF-LINE LAYER IN COMBINATION WITH DECOUPLING CAPACITORS - A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors. | 03-10-2016 |
20160079167 | TIE-OFF STRUCTURES FOR MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS, AND RELATED METHODS - Tie-off structures for middle-of-line (MOL) manufactured integrated circuits, and related methods are disclosed. As a non-limiting example, the tie-off structure may be used to tie-off a drain or source of a transistor to the gate of the transistor, such as provided in a dummy gate used for isolation purposes. In this regard in one aspect, a MOL stack is provided that includes a metal gate connection that is coupled to a metal layer through metal structure disposed in and above a dielectric layer above a gate associated with the metal gate connection. By coupling the metal gate connection to the metal layer, the gate of a transistor may be coupled or “tied-off” to a source or drain element of the transistor. This may avoid the need to etch the metal gate connection provided below the dielectric layer to provide sufficient connectivity between the metal layer and the metal gate connection. | 03-17-2016 |
20160079175 | MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS (ICs) EMPLOYING LOCAL INTERCONNECTS OF METAL LINES USING AN ELONGATED VIA, AND RELATED METHODS - Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes. | 03-17-2016 |
Patent application number | Description | Published |
20080207635 | Heterocyclic compounds useful in the treatment of neoplastic diseases, inflammatory disorders and immunomodulatory disorders - The present invention provides compounds capable of modulating tyrosine kinases, compositions comprising the compounds and methods of their use. | 08-28-2008 |
20090183283 | RICE PROMOTERS FOR REGULATION OF PLANT EXPRESSION - The present invention provides promoters from plants capable of driving gene expression in plant cells. The promoters vary in strength and in tissue specificity, and can be used to facilitate the development of transgenic plants in which tissue preferred expression, constitutive expression, and the strength of transgene expression is either more or less critical. | 07-16-2009 |
20100287671 | Stress-regulated genes of plants, transgenic plants containing same, and methods of use - Clusters of plant genes that are regulated in response to one or more stress conditions are provided, as are isolated plant stress-regulated genes, including portions thereof comprising a coding sequence or a regulatory element, and to consensus sequences comprising a plant stress-regulated regulatory element. In addition, a recombinant polynucleotide, which includes a plant stress-regulated gene, or functional portion thereof, operatively linked to a heterologous nucleotide sequence, is provided, as are transgenic plants, which contain a plant stress-regulated gene or functional portion thereof that was introduced into a progenitor cell of the plant. Also provided are methods of using a plant stress-regulated gene to confer upon a plant a selective advantage to a stress condition, methods of identifying an agent that modulates the activity of a plant stress-regulated regulatory element, and methods of determining whether a plant has been exposed to a stress. | 11-11-2010 |
20110218156 | MOLECULAR ENTITIES FOR BINDING, STABILIZATION AND CELLULAR DELIVERY OF NEGATIVELY CHARGED MOLECULES - In accordance with the present invention, it has been discovered that the uptake of negatively charged entities into cells can be enhanced by noncovalently associating such charged entities with molecular entities comprising an amphiphilic core with positively charged arms, wherein a plurality of lipophilic (e.g., bile acid) moieties are covalently attached to the positively charged arms. The molecular entities form well defined stoichiometric complexes with negatively charged entities. Various compositions and methods for stabilizing anionic charged entities and for enhancing the cellular uptake of any anionic charged entities, e.g. double-stranded or hairpin nucleic acid, are provided. | 09-08-2011 |
20120149653 | MULTIFUNCTIONAL LINKERS AND METHODS FOR THE USE THEREOF - In accordance with the present invention, novel multifunctional compounds have been developed which have orthogonal reactive groups thereon, thereby facilitating preparation of compounds having multiple functional properties (e.g., a targeting moiety and a biologically active moiety). Such constructs are useful for a variety of applications, e.g., for the delivery of biologically compatible materials, and release thereof in active form. Therefore, in accordance with the present invention, there are provided multifunctional linkers of defined structure, as well as various derivatives thereof bearing one or more biologically active components thereon. Also provided in accordance with the present invention are methods for the preparation of such constructs, as well as various uses thereof. | 06-14-2012 |
20120149732 | MULTIFUNCTIONAL LINKERS AND METHODS FOR THE USE THEREOF - In accordance with the present invention, novel multifunctional compounds have been developed which have orthogonal reactive groups thereon, thereby facilitating preparation of compounds having multiple functional properties (e.g., a targeting moiety and a biologically active moiety). Such constructs are useful for a variety of applications, e.g., for the delivery of biologically compatible materials, and release thereof in active form. Therefore, in accordance with the present invention, there are provided multifunctional linkers of defined structure, as well as various derivatives thereof bearing one or more biologically active components thereon. Also provided in accordance with the present invention are methods for the preparation of such constructs, as well as various uses thereof. | 06-14-2012 |
20130053376 | NOVEL TYROSINE KINASE INHIBITORS - Provided are compounds of the formula (I): or a stereoisomer, tautomer, salt, hydrate or prodrug thereof that modulate tyrosine kinase activity, compositions comprising the compounds and methods of their use. | 02-28-2013 |
20150105539 | Drug-Conjugates, Conjugation Methods, and Uses Thereof - In one aspect, an active agent-conjugate, methods of preparing the active agent-conjugate, and uses thereof is provided. | 04-16-2015 |
20150105540 | DRUG-CONJUGATES WITH A TARGETING MOLECULE AND TWO DIFFERENT DRUGS - There is disclosed an improved ADC (antibody drug conjugate) type composition having at least two different drug payloads conjugated to a single targeting protein. More specifically, the present disclosure attaches a first drug conjugate to a dual Cysteine residue on a targeting protein and a second drug conjugate with a different drug to a Lys residue on the targeting protein. | 04-16-2015 |
20150141646 | Drug-Conjugates, Conjugation Methods, and Uses Thereof - In certain aspects, compounds and uses thereof are provided. In certain aspects, compound-conjugates and uses thereof are provided. | 05-21-2015 |
20160067350 | Drug-Conjugates, Conjugation Methods, and Uses Thereof - In one aspect, an active agent-conjugate, methods of preparing the active agent-conjugate, and uses thereof is provided. | 03-10-2016 |
Patent application number | Description | Published |
20120275321 | APPARATUS AND METHOD FOR ARBITRATION OF UPDATES PROVIDED TO A UNIVERSAL INTEGRATED CIRCUIT CARD - Systems and methodologies are described that determine whether to communicate an update message to a UICC. A UE may be equipped a status update message from at least one of a first radio access technology (RAT) module supporting a first RAT and a second RAT module supporting a second RAT. The first RAT and the second RAT are different. Further, the UE may be equipped to determine whether to generate a universal integrated circuit card (UICC) update message to update a UICC by applying one or more RAT arbitration factors to the received status update message. The UICC includes current UICC status information associated with a current RAT. A status update message may include, a service status, RAT information, and location information, and the UE may apply the RAT arbitration factors to at least a portion of the status update message. | 11-01-2012 |
20140003248 | SYSTEMS AND METHODS FOR BEARER INDEPENDENT PROTOCOL GATEWAY OPTIMIZATION | 01-02-2014 |
20140066120 | APPARATUS AND METHOD WITH ROUTING LOGIC FOR COMMUNICATIONS BETWEEN MULTIPLE BASEBAND MODEMS AND A UNIVERSAL INTEGRATED CIRCUIT CARD - Aspects of the present disclosure are directed to a user equipment having a universal integrated circuit card (UICC), multiple baseband modems, and routing logic for handling communications between the UICC and the baseband modems, and methods for operating the user equipment in which the routing logic arbitrates communication between the UICC and the baseband modems in accordance with arbitration logic. Other aspects, embodiments, and features are also claimed and described. | 03-06-2014 |
20140141760 | SYSTEMS, APPARATUS, AND METHODS FOR MANAGING INFORMATION IN A SMART STORAGE DEVICE - This disclosure provides systems, methods, and apparatus for refreshing information stored on a smart storage device. In one aspect a smart storage device is provided that is configured to be coupled to a wireless communications apparatus operating in a wireless communications network. The smart storage device includes a memory configured to store network access information for accessing services of the network. The smart storage device further includes a controller configured to send a message to the wireless communications apparatus including data notifying the wireless communications apparatus of an update to the network access information. The data further includes a command that the wireless communications apparatus suspend an active operation of the wireless communications apparatus and initiate updating information managed by the wireless communications apparatus based on one or more conditions. The updating of the information is based on at least a portion of the updated network access information. Other aspects, embodiments, and features are also claimed and described. | 05-22-2014 |
20140220949 | APPARATUS AND METHOD FOR OPTIMAL SCHEDULING OF ENVELOPE UPDATES TO SIM CARD - Aspects of the present disclosure are directed to an apparatus and methods that may improve scheduling of envelope updates to a SIM. An apparatus for wireless communication is configured to receive a plurality of updates in one or more envelope commands, categorize the updates into a plurality of groups having respective priorities, and send the updates to a SIM at the apparatus in order according to the respective priorities. Other aspects, embodiments, and features are also claimed and described. | 08-07-2014 |
20150072736 | APPARATUS AND METHODS FOR NEGOTIATING PROACTIVE POLLING INTERVAL - Aspects of the present disclosure are directed to a polling interval negotiation scheme between a universal integrated circuit card (UICC) and a wireless terminal. A wireless terminal and a UICC are communicating at a first polling interval. The wireless terminal may send a proposed polling interval to the UICC. The wireless terminal determines a response of the UICC to the proposed polling interval, and communicates with the UICC at a second polling interval based on the response of the UICC. | 03-12-2015 |
Patent application number | Description | Published |
20120120789 | SYSTEMS AND METHODS FOR IMPROVING CIRCUIT SWITCHED FALLBACK PERFORMANCE - Methods and apparatus for improving Circuit Switched (CS) Fallback performance, such as in an LTE network, are described. In one aspect, a UE may perform a RAU procedure before performing a CS call setup procedure when the UE has camped on a Non-DTM GERAN target after failing to access a redirection target. In another aspect, an MME may determine whether to perform a PS suspension based on an ISR status associated with a user terminal. In another aspect, an eNB may send information associated with a PS suspension to a user terminal. | 05-17-2012 |
20120269110 | QUALITY OF SERVICE CONTROL IN A MULTICAST TRANSMISSION - A network entity may dynamically control Quality-of-Service (QoS) for a multicast transmission in a wireless communications system, by initiating a multicast transmission having an initial QoS, and later during the multicast transmission, generating an updated QoS for the multicast transmission. The network entity may generate the updated QoS in response to a network load factor for a multicast area aggregated from base stations in the area. The network load factor may indicate a measure of aggregate available bandwidth in the multicast area. The network entity may provide the updated QoS to mobile entities receiving the multicast transmission, which may process a subsequent portion of multicast content according to the updated QoS. | 10-25-2012 |
20140059662 | Shared circuit switched security context - Creation of update of a security context between user equipment and MSC/VLR (Mobile Switching Centre/Visitor Location Register) for circuit switched domain services is provided. The creation or update is based on conversion of the security context used in an evolved Universal Terrestrial Radio Access Network (E-UTRAN) in the Mobility Management Entity (MME) to a security context for the circuit switched domain target system and transferring it to a MSC/VLR. When user equipment is moved from E-UTRAN to GSM EDGE Radio Access Network/Universal Terrestrial Radio Access Network (GERAN/UTRAN), a MME does not need to perform authentication and key agreement procedures to establish shared circuit switched security context for the user equipment. | 02-27-2014 |
20140105125 | CRITERIA FOR UE-INITIATED BEARER DEACTIVATION WHEN MAXIMUM NUMBER OF ACTIVE BEARERS HAS BEEN REACHED - A UE determines a need to deactivate one or more bearer contexts. The UE then selects for deactivation one or more active bearer contexts based on a context selection criteria, to avoid exceeding a maximum number of allowable active bearer contexts for the UE. The context selection criteria may relate to one or more of: current usage of active bearer contexts, information from applications associated with active bearer contexts, priority level of applications associated with active bearer contexts, order of active bearer context creation, measure of data activity through active bearer contexts, quality of service associated with active bearer contexts, type of service, e.g. voice or data, for which bearer contexts were activated, bandwidth allocations of active bearer contexts, a criteria predefined by the UE, network or user, or a random selection. Once one or more active bearer contexts have been selected, the UE deactivates the selected active bearer contexts. | 04-17-2014 |
Patent application number | Description | Published |
20110053897 | COMPOUNDS AND COMPOSITIONS AS SYK KINASE INHIBITORS - Provided herein area novel class of compounds, pharmaceutical compositions comprising such compounds and methods of using such compounds to treat or prevent diseases or disorders associated with abnormal or deregulated Syk kinase activity. | 03-03-2011 |
20110172278 | COMPOUNDS AND METHODS FOR MODULATING G PROTEIN-COUPLED RECEPTORS - The invention provides compounds, pharmaceutical compositions comprising such compounds and methods of using such compounds to treat or prevent diseases or disorders associated with or mediated by G protein-coupled receptors, in particular G protein-coupled receptor 120. | 07-14-2011 |
20110190264 | COMPOUNDS AND COMPOSITIONS AS KINASE INHIBITORS - The invention relates to triazine and pyrimidine derivatives having Formula (1) or (2), and methods for using such compounds. For example, the compounds of the invention may be used to treat, ameliorate or prevent a condition which responds to inhibition of anaplastic lymphoma kinase (ALK) activity, c-ros oncogene (ROS), insulin-like growth factor (IGF-IR), and/or insulin receptor (InsR) or a combination thereof. | 08-04-2011 |
20120184526 | COMPOUNDS AND COMPOSITIONS AS SYK KINASE INHIBITORS - Provided herein are a novel class of compounds, pharmaceutical compositions comprising such compounds and methods of using such compounds to treat or prevent diseases or disorders associated with abnormal or deregulated Syk kinase activity. | 07-19-2012 |
20130096165 | COMPOUNDS AND METHODS FOR MODULATING G PROTEIN-COUPLED RECEPTORS - The invention provides compounds, pharmaceutical compositions comprising such compounds and methods of using such compounds to treat or prevent diseases or disorders associated with or mediated by G protein-coupled receptors, in particular G protein-coupled receptor 120. | 04-18-2013 |
20130210769 | COMPOUNDS AND COMPOSITIONS AS INHIBITORS OF CANNABINOID RECEPTOR 1 ACTIVITY - The invention provides compounds, pharmaceutical compositions comprising such compounds and methods of using such compounds to treat or prevent diseases or disorders associated with the activity of Cannabinoid Receptor 1 (CB1). | 08-15-2013 |
Patent application number | Description | Published |
20090172452 | System and Method of Leakage Control in an Asynchronous System - Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage. | 07-02-2009 |
20100039136 | Gate Level Reconfigurable Magnetic Logic - A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power. | 02-18-2010 |
20110050334 | Integrated Voltage Regulator with Embedded Passive Device(s) - A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate. | 03-03-2011 |
20110215863 | Integrated Voltage Regulator with Embedded Passive Device(s) - A method of supplying voltage to a die mounted on a packaging substrate includes mounting an active portion of a voltage regulator on the packaging substrate. The method also includes coupling the active portion of the voltage regulator to at least one passive component at least partially embedded in the packaging substrate and coupling the die to the at least one passive component. Mounting the active portion of the voltage regulator includes mounting the die on the packaging substrate where the die includes the active portion of the voltage regulator. | 09-08-2011 |
20110317387 | Integrated Voltage Regulator with Embedded Passive Device(s) for a Stacked IC - A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on. | 12-29-2011 |
20120109356 | Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection - In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit. | 05-03-2012 |
20120112809 | METHOD AND DIGITAL CIRCUIT FOR GENERATING A WAVEFORM FROM STORED DIGITAL VALUES - In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path. | 05-10-2012 |
20120293972 | Integrated Voltage Regulator Method with Embedded Passive Device(s) - A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias. | 11-22-2012 |
20130033329 | System and Method of Controlling Gain of an Oscillator - A circuit includes a controllable oscillator and a controller coupled to the controllable oscillator. The controller is configured to provide a current control and a gain control to the controllable oscillator. The gain control is configured to change a gain of the controllable oscillator during a calibration process. | 02-07-2013 |
20130120029 | HIGH-SPEED PRE-DRIVER AND VOLTAGE LEVEL CONVERTER WITH BUILT-IN DE-EMPHASIS FOR HDMI TRANSMIT APPLICATIONS - In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver. | 05-16-2013 |
20130120036 | APPARATUS AND METHOD FOR RECOVERING BURST-MODE PULSE WIDTH MODULATION (PWM) AND NON-RETURN-TO-ZERO (NRZ) DATA - A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits. | 05-16-2013 |
20130191679 | DUAL MODE CLOCK/DATA RECOVERY CIRCUIT - A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst. | 07-25-2013 |
20130216014 | AUTOMATIC DETECTION AND COMPENSATION OF FREQUENCY OFFSET IN POINT-TO-POINT COMMUNICATION - Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency. | 08-22-2013 |
20140062559 | SYSTEM AND METHOD OF ADJUSTING A CLOCK SIGNAL - A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal. | 03-06-2014 |
20140098843 | DIGITALLY CONTROLLED JITTER INJECTION FOR BUILT IN SELF-TESTING (BIST) - A digitally controlled jitter injection apparatus for built in self-testing includes a transceiver circuit having a transmitter circuit and a receiver circuit. The digitally controlled jitter injection apparatus also includes a generator that generates a composite jitter including multi-tone jitter components. The digitally controlled jitter injection apparatus also includes a processor operable to digitally inject the composite jitter into a receiver circuit and/or a transmitter circuit of the transceiver circuit. | 04-10-2014 |
20150235952 | INTEGRATED VOLTAGE REGULATOR WITH EMBEDDED PASSIVE DEVICE(S) FOR A STACKED IC - A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on. | 08-20-2015 |
20150280695 | SYSTEMS AND METHODS FOR COMMON MODE LEVEL SHIFTING - A common mode voltage level shifting circuit including: input nodes configured to receive a differential signal with a first common mode voltage, a pair of shunt capacitors coupled between the input nodes and a corresponding pair of output nodes, a threshold voltage circuit, including the output nodes, coupled to the differential signal though the shunt capacitors, the threshold voltage circuit configured to provide a second common mode voltage for the differential signal at the output nodes, and current sources that are controlled according to a level of the first common mode voltage, the current sources coupled to the output nodes to effect the second common mode voltage. | 10-01-2015 |
20150303910 | PULSE-WIDTH MODULATION DATA DECODER - Systems and methods for decoding pulse-width modulated (PWM) data are disclosed. An example decoder filters a data input signal with a one-sided pulse filter. The one-sided pulse filter suppresses short pulses on the data input signal and passes long pulses. The example decoder latch the filtered data signal at the end of each bit time of the data input signal. The duration of pulses that are suppressed by the one-sided pulse filter can be calibrated to compensate for circuit variations and to allow the decoder to operate at various data rates. The decoder can be implemented in a small integrated circuit area and can be power efficient. | 10-22-2015 |
20150304134 | SERDES VOLTAGE-MODE DRIVER WITH SKEW CORRECTION - A driver circuit for transmitting serial data on a communication link combines voltage-mode and current-mode drivers. The driver circuit uses a voltage-mode driver as the main output driver. One or more auxiliary current-mode drivers are connected in parallel with the voltage-mode driver to adjust the output signal by injecting currents into the outputs. The voltage-mode driver supplies most of the output drive. Thus, the output driver circuit can provide the power efficiency benefits associated with voltage-mode drivers. The current-mode drivers can provide, for example, pre-emphasis, level adjustment, skew compensation, and other modifications of the output signals. Thus, the driver circuit can also provide the signal adjustment abilities associated with current-mode drivers. | 10-22-2015 |
20150358008 | Linearity of Phase Interpolators using Capacitive Elements - A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each branch including a differential pair of transistors connected at source terminal to form a source node; a plurality of tail current sources, each tail current source coupled to one of the source nodes; and a plurality of coupling capacitors, each coupling capacitor coupled between the source nodes in two adjacent branches of the plurality of branches. | 12-10-2015 |
20150358148 | Linearity of Phase Interpolators by Combining Current Coding and Size Coding - A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors. | 12-10-2015 |
20160079942 | COMMON-GATE AMPLIFIER FOR HIGH-SPEED DC-COUPLING COMMUNICATIONS - In one embodiment, a receiver comprises a differential common-gate amplifier having a differential input and a differential output, wherein the differential input comprises a first input and a second input, and the differential common-gate amplifier is configured to amplify an input differential signal at the differential input into an amplified differential signal at the differential output. The receiver also comprises a common-mode voltage sensor configured to sense a common-mode voltage of the input differential signal, a replica circuit configured to generate a replica voltage that tracks a direct current (DC) voltage at at least one of the first and second inputs, and a comparator configured to compare the sensed common-mode voltage with the replica voltage, and to adjust a first bias voltage input to the differential common-gate amplifier based on the comparison, wherein the DC voltage depends on the first bias voltage. | 03-17-2016 |
20160099678 | VCO, PLL, AND VARACTOR CALIBRATION - In one aspect, a VCO is provided. The VCO includes an inductor, a voltage-controlled capacitive element configured to operate with the inductor to generate an oscillating signal, a voltage supply configured to provide a plurality of voltages to the voltage-controlled capacitive element in a calibration mode, and a control circuit configured to store frequency information indicating frequencies of the oscillating signal in response to the plurality of voltages being provided to the voltage-controlled capacitive element. In another aspect, a PLL is provided. The PLL includes means for selecting, in an open loop configuration, a capacitance of a capacitor based on a target frequency and means for selecting, in a closed loop configuration, an operation voltage of a voltage-controlled capacitive element based on the capacitance of the capacitor. | 04-07-2016 |