Patent application number | Description | Published |
20130318156 | DYNAMIC INFORMATION STREAMS IN A SOCIAL NETWORK PLATFORM - The techniques, methods and systems described herein facilitate the automated discovery and presentation of content created, published or otherwise made public by “experts” and key influencers on particular topics. As such, users that may be interested in particular topics but may not know who to connect with in order to receive the most pertinent information can receive highly-relevant information. Embodiments of the invention use topics of interest identified by the user and/or automatically identifies topics based on previous postings, communication, contacts, etc. Individuals, companies, organizations and other entities that have been recognized as highly influential in those topics are identified and, without explicit actions by the user, adds content generated by the influential entities to the user's content data feed. | 11-28-2013 |
20140040377 | DYNAMIC INFORMATION STREAMS IN A SOCIAL NETWORK PLATFORM - The techniques, methods and systems described herein facilitate the automated discovery and presentation of content created, published or otherwise made public by “experts” and key influencers on particular topics. As such, users that may be interested in particular topics but may not know who to connect with in order to receive the most pertinent information can receive highly-relevant information. Embodiments of the invention use topics of interest identified by the user and/or automatically identifies topics based on previous postings, communication, contacts, etc. Individuals, companies, organizations and other entities that have been recognized as highly influential in those topics are identified and, without explicit actions by the user, adds content generated by the influential entities to the user's content data feed. | 02-06-2014 |
Patent application number | Description | Published |
20110261721 | METHOD AND SYSTEM ARCHITECTURE FOR A SELF ORGANIZING NETWORK - A method and system architecture for a self-organizing network (SON) includes a first cell having a first user equipment classifier for determining one of cell edge and cell central. The SON also includes a second cell having a second user equipment classifier for determining one of cell edge and cell central. The system architecture and method provide a first transmit time interval (TTI) schema for user equipment within the area of coverage associated with the first cell and a TTI schema for user equipment within the area of coverage associated with the second cell, the second TTI schema differing from the first TTI schema. The user equipment is classified as cell centre or cell edge in dependence upon at least one of QoS requirement, geometry, periodic PSMM and CQI reports. The TTI schemas are used for “cell edge” user equipment by the respective cells. | 10-27-2011 |
20120088517 | AUTONOMOUS FRACTIONAL TIME REUSE - Autonomous fractional time reuse is provided. In some embodiments, autonomous fractional time reuse includes determining a number of neighboring base stations of a base station in a heterogeneous network; and pseudo randomly selecting one or more Fractional Time Reuse (FTR) slots for transmission by the base station. In some embodiments, the one or more FTR slots are autonomously selected by the base station without coordinating the selection of the one or more FTR slots with one or more of the neighboring base stations. | 04-12-2012 |
20150065189 | AUTONOMOUS POWER ADAPTATION IN A HETEROGENEOUS CELLULAR ENVIRONMENT - Autonomous power adaptation in a heterogeneous cellular environment is disclosed. In some embodiments, autonomous power adaptation for a first small area cellular device in a heterogeneous cellular environment includes collecting received signal strength information for one or more neighboring large area cellular devices and one or more neighboring small area cellular devices; and determining a maximum transmit power for the first small area cellular device that minimizes interference with the one or more neighboring large area cellular devices and the one or more small area cellular devices, in which determining the maximum transmit power for the first small area cellular device that minimizes interference with the one or more neighboring large area cellular devices and the one or more small area cellular devices includes prioritizing the one or more neighboring large area cellular devices over the one or more neighboring small area cellular devices. | 03-05-2015 |
Patent application number | Description | Published |
20090040136 | ESD PROTECTION FOR MEMS DISPLAY PANELS - A MEMS (Microelectromechanical system) device is described. The device includes an array of MEMS elements with addressing lines and MEMS switches configured to selectively connect the addressing lines to a ground or other potential in the event of an over-voltage, such as during an ESD event. The arrangement is particularly advantageous for protecting the array, because the MEMS switches can be formed using substantially the same processing steps which are used to form the array. | 02-12-2009 |
20130100143 | STACKED VIAS FOR VERTICAL INTEGRATION - This disclosure provides systems, methods and apparatus for a via structure. In one aspect, an apparatus includes a substrate and a first electromechanical systems device on a surface of the substrate. The first electromechanical systems device includes a first metal layer and a second metal layer. A first via structure can be included on the surface of the substrate. The first via structure includes the first metal layer, the second metal layer, and a third metal layer. The first metal layer of the first electromechanical systems device may be the same metal layer as the first metal layer of the first via structure. | 04-25-2013 |
20140192060 | CONTROLLING MOVABLE LAYER SHAPE FOR ELECTROMECHANICAL SYSTEMS DEVICES - Systems, methods and apparatus are provided for controlling launch effects of movable layers in electromechanical systems (EMS) devices. First and second EMS devices with first and second step creating layers are positioned over a substrate and spaced, by different gaps, from the movable layers of the EMS devices. The movable layers of the first and second EMS devices include steps having different heights and/or different edge spacing from the center of an anchoring region of each EMS device. The different steps can provide different launch effects for different EMS devices, and if the same thickness of sacrificial material is used for the different devices, the different launch effects can be responsible for different gap heights in the unbiased conditions. | 07-10-2014 |
20150346478 | Protection of Thin Film Transistors in a Display Element Array from Visible and Ultraviolet Light - A display assembly includes an array of display elements disposed between a first substrate and a second substrate, the array of display elements including one or more thin film transistors (TFTs). A black mask arrangement is disposed between the first substrate and the second substrate, the black mask arrangement being configured to prevent light entering the display assembly from reaching the TFTs. | 12-03-2015 |
Patent application number | Description | Published |
20090044273 | CIRCUITS AND METHODS FOR EFFICIENT DATA TRANSFER IN A VIRUS CO-PROCESSING SYSTEM - Various embodiments of the present invention circuits and methods for improved virus processing. As one example, such methods may include providing a system memory, a general purpose processor and a virus co processor. The methods further include receiving a data segment at the general purpose processor, and storing the data segment to the system memory using virtual addresses. The date segment is accessed from the system memory by the virus co processor using the virtual addresses. The virus co processor then scans the date segment for viruses and returns results. | 02-12-2009 |
20090304029 | VIRTUAL MEMORY PROTOCOL SEGMENTATION OFFLOADING - Methods and systems for a more efficient transmission of network traffic are provided. According to one embodiment, a method is provided for performing segmentation offloading, such as TCP segmentation offloading (TSO). An interface performs direct virtual memory addressing of a user memory space of a system memory on behalf of a network processor to fetch payload data originated by a user process running on a host processor. Then, the network processor segments the payload data across one or more packets. | 12-10-2009 |
20090307363 | NETWORK PROTOCOL REASSEMBLY ACCELARATION - Methods and systems are provided for network protocol reassembly acceleration. According to one embodiment, an incoming packet is received at a network interface. Payload data from the packet is written by a memory interface to a physical page within a system memory on behalf of the network interface based on a sequence number associated with the incoming packet and by obtaining a physical address from a virtual memory map corresponding to an incoming session with which the packet is associated. After the physical page is full, the physical page is made accessible to a user process being executed by a processor associated with the system memory by remapping the physical page through a paging table used by the user process. | 12-10-2009 |
20120317646 | VIRUS CO-PROCESSOR INSTRUCTIONS AND METHODS FOR USING SUCH - Circuits and methods for detecting, identifying and/or removing undesired content are provided. According to one embodiment, a method for virus processing is provided. A general purpose processor receives and stores a data segment to a first memory at a virtual address. The first memory contains paging data structures for translating virtual addresses to physical addresses. The general purpose processor directs a virus processing hardware accelerator to scan the data segment based on virus signatures compiled for the virus processing hardware accelerator and stored in a second memory. The first memory includes a first virus signature compiled for the general purpose processor. The virus processing hardware accelerator retrieves the data segment by accessing the first memory based on the virtual address and cached information, stored within one or more translation lookaside buffers local to the virus processing hardware accelerator, relating to most recently used entries of the paging data structures. | 12-13-2012 |
20130152203 | OPERATION OF A DUAL INSTRUCTION PIPE VIRUS CO-PROCESSOR - Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a method for virus processing content objects is provided. A content object is stored within a system memory by a general purpose processor using a virtual address. Most recently used entries of a page directory and a page table of the system memory are cached within a translation lookaside buffer (TLB) of a virus co-processor. Instructions are read from a virus signature memory of the co-processor. Those of a first type are assigned to a first of multiple instruction pipes of the co-processor. The first instruction pipe executes an instruction including accessing a portion of the content object by performing direct virtual memory addressing of the system memory using a physical address derived based on the virtual address and the TLB and comparing it to a string associated with the instruction. | 06-13-2013 |
20130215904 | VIRTUAL MEMORY PROTOCOL SEGMENTATION OFFLOADING - Methods and systems for a more efficient transmission of network traffic are provided. According to one embodiment, a user process of a host processor requests a network driver to store payload data within a system memory. The network driver stores (i) payload buffers each containing therein at least a subset of the payload data and (ii) buffer descriptors each containing therein information indicative of a starting address of a corresponding payload buffer within a user memory space. A network processor transmits onto a network the payload data within multiple transport layer protocol packets by (i) causing a network interface to retrieve the payload data from the payload buffers by performing direct virtual memory addressing of the user memory space using the buffer descriptors and information contained within a translation data structure stored within the system memory; and (ii) segmenting the payload data across the transport layer protocol packets. | 08-22-2013 |
20140096254 | EFFICIENT DATA TRANSFER IN A VIRUS CO-PROCESSING SYSTEM - Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a method for virus co-processing is provided. A general purpose processor stores a data segment to its system memory using a virtual address. The system memory has stored therein a page directory and a page table containing information for translating virtual addresses to physical addresses within a physical address space of the system memory. A virus processing hardware accelerator translates the virtual address of the data segment to a physical address of the data segment based on the page directory and the page table. The hardware accelerator accesses the data segment based on the physical address. The hardware accelerator scans the data segment for viruses by executing multiple pattern comparisons against the data segment. The hardware accelerator returns a result of the scanning to the general purpose processor via the system memory. | 04-03-2014 |
20140143876 | VIRUS CO-PROCESSOR INSTRUCTIONS AND METHODS FOR USING SUCH - Circuits and methods for detecting, identifying and/or removing undesired content are provided. According to one embodiment, a method for virus processing is provided. A data segment is received by a general purpose processor coupled to a virus co-processor and a memory via an interconnect bus. The memory includes a first signature and a second signature. The first includes a primitive instruction and a Content Pattern Recognition (CPR) instruction stored at contiguous locations in the memory and compiled for hardware execution on the co-processor. The second is compiled for software execution. The data segment is scanned by the general purpose processor by applying the second signature against the data segment. The co-processor is directed by the general purpose processor to scan the data segment by applying the first signature against the data segment by storing the data segment to the memory and indicating a request for a scan to the co-processor. | 05-22-2014 |
20140351937 | VIRUS CO-PROCESSOR INSTRUCTIONS AND METHODS FOR USING SUCH - Circuits and methods for detecting, identifying and/or removing undesired content are provided. According to one embodiment, a method for virus processing is provided. A virus signature file that includes multiple virus signatures capable of detecting and identifying a variety of known viruses is downloaded by a general purpose processor. It is determined by the general purpose processor whether a virus co-processor is coupled to the general purpose processor. When the virus co-processor is determined to be coupled to the general purpose processor, then it is further determined by the general purpose processor which virus signatures are supported by the virus co-processor (“CP-supported virus signatures”). The CP-supported virus signatures are transferred to a memory associated with the virus co-processor. The virus co-processor is directed by the general purpose processor to perform a virus scan based on the supported virus signatures. | 11-27-2014 |
20150110125 | VIRTUAL MEMORY PROTOCOL SEGMENTATION OFFLOADING - Methods and systems for a more efficient transmission of network traffic are provided. According to one embodiment, payload data originated by a user process running on a host processor of the computer system is fetched by an interface of the computer system by performing direct virtual memory addressing of a user memory space of a system memory of the computer system on behalf of a network processor of the computer system. The direct virtual memory addressing maps a physical address of the payload data to a virtual address. The payload data is segmented by the network processor across one or more packets. | 04-23-2015 |
20150269381 | EFFICIENT DATA TRANSFER IN A VIRUS CO-PROCESSING SYSTEM - Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a processor maintains a page directory and a page table within a system memory that contain information for translating virtual addresses to physical addresses. Virus processing of a content object is offloaded to a hardware accelerator coupled to the processor by storing scanning parameters, including the content object and a type of the content object, to the memory using one or more virtual addresses and indicating to the hardware accelerator that the content object is available for processing. Responsive thereto, the hardware accelerator: (i) translates the virtual addresses to corresponding physical addresses based on the page directory and the page table; (ii) accesses the scanning parameters based on the physical addresses; (iii) scans the content object for viruses by applying multiple virus signatures; and (iv) returns a result of the scanning to the processor. | 09-24-2015 |