Patent application number | Description | Published |
20110266677 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises; providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits. | 11-03-2011 |
20120061736 | Transistor and Method for Forming the Same - The present invention relates to a stress-enhanced transistor and a method for forming the same. The method for forming the transistor according to the present invention comprises the steps of forming a mask layer on a semiconductor substrate on which a gate has been formed, so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so as to expose at least a portion of each of a source region and a drain region; amorphorizing the exposed portions of the source region and the drain region; removing the mask layer; and annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region. | 03-15-2012 |
20120104473 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations. | 05-03-2012 |
20120104474 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer. | 05-03-2012 |
20120104486 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein only the source region comprises at least one dislocation. The method for forming a transistor according to the present invention comprises forming a mask layer on a semiconductor substrate on which a gate has been formed so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer to only expose at least a portion of a source region; performing a first ion implantation to the exposed portion of the source region; and annealing the semiconductor substrate so as to form a dislocation in the exposed portion of the source region. | 05-03-2012 |
20120168863 | Semiconductor Structure and Method for Manufacturing the Same - Semiconductor structure and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device is formed on an SOI substrate comprising an SOI layer, a buried insulating layer, a buried semiconductor layer and a semiconductor substrate from top to bottom, and comprises: source/drain regions formed in the SOI layer; a gate formed on the SOI layer, wherein the source/drain regions are located at both sides of the gate; a back gate region formed by a portion of the buried semiconductor layer which is subjected to resistance reduction; and a first isolation structure and a second isolation structure which are located at both sides of the source/drain regions and extend into the SOI substrate; wherein the first isolation structure and the second isolation structure laterally adjoin the SOI layer at a first side surface and a second side surface respectively; the first isolation structure laterally adjoins the buried semiconductor layer at a third side surface; and the third side surface is located between the first side surface and the second side surface. | 07-05-2012 |
20120193531 | METHOD FOR LINE WIDTH MEASUREMENT - A method for line width measurement, comprising: providing a substrate, wherein a raised line pattern is formed on a surface of the substrate, and the line pattern has a width; forming a first measurement structure and a second measurement structure on opposite sidewalls of the line pattern in the width direction of the line pattern; removing the line pattern; and measuring the spacing between the first measurement structure and the second measurement structure, and obtaining the width of the line pattern by subtracting a predetermined offset from the spacing. The present invention facilitates to reduce the uncertainty associated with the measuring process and to improve the measurement precision. | 08-02-2012 |
20120305941 | WELL REGION FORMATION METHOD AND SEMICONDUCTOR BASE - A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to till the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to till the grooves. | 12-06-2012 |
20130323894 | Transistor and Method for Forming the Same - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer. | 12-05-2013 |