Patent application number | Description | Published |
20090111220 | COATED LEAD FRAME - A lead frame having a coating of organic compounds on its lead fingers prevents tin and flux from contaminating the lead fingers after die attach. The coating is removed prior to wire bonding. The coating allows for reliable second bonds (bond between wires and lead fingers) to be formed, decreasing the likelihood of non-stick and improving wire peel strength. | 04-30-2009 |
20100248426 | METHOD OF MAKING CHIP-ON-LEAD PACKAGE - A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided. | 09-30-2010 |
20100314754 | METHOD OF FORMING WIRE BONDS IN SEMICONDUCTOR DEVICES - A method of forming a wire bond in a semiconductor device includes forming a first bump of a first composition proximate to a probe mark on a bond pad. A second bump of the first composition is formed adjacent to the first bump such that the first and second bumps are formed away from the probe mark. A wire of a second composition that is harder than the first composition is attached on top of the first and second bumps to form an interconnection. | 12-16-2010 |
20100317152 | METHOD FOR ASSEMBLING STACKABLE SEMICONDUCTOR PACKAGES - A method for assembling a stackable semiconductor package includes providing a substrate having a first surface and a second surface. The first surface includes bond pads and one or more die pads. Conductive bumps are formed on the bond pads and one or more semiconductor dies are attached to the one or more die pads. The first surface of the substrate, the semiconductor dies and the conductive bumps are placed in a side-gate molding cast and a mold material is supplied to the first surface of the substrate to form a stackable semiconductor package. Similarly formed semiconductor packages may be stacked, one on another to form a stacked semiconductor package. | 12-16-2010 |
20110108967 | SEMICONDUCTOR CHIP GRID ARRAY PACKAGE AND METHOD FOR FABRICATING SAME - A semiconductor chip grid array package includes a die attach pad and a plurality of connector pads. A semiconductor die is mounted on the die attach pad, the semiconductor die having external connection terminals electrically connected respectively to the connector pads. An encapsulating material encapsulates the die and connector pads. A stud protrudes from each of the connector pads for providing an external electrical contact for the semiconductor chip grid array package. Each of the connector pads and respective studs are formed from an electrically conductive sheet. The connector pads have a thickness of at least 60% of the thickness of the conductive sheet and the respective studs have a thickness of no more than 40% of the thickness of the conductive sheet. | 05-12-2011 |
20110263077 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES INCLUDING SAW SINGULATION - A method of assembling semiconductor devices for surface mounting includes forming an array of lead frames in which supporting frame structures of adjacent lead frames include an intermediate common bar connecting on both its sides with sets of leads of the respective adjacent lead frames. The semiconductor devices are singulated by sawing through the leads on each side of the common bars without sawing the common bars longitudinally. The material sawn off from the common bars in a first direction is removed by washing it away before sawing off the intermediate common bars that run in an orthogonal direction. The supporting frame structures include bars surrounding the array and singulation includes sawing beside the surrounding bars to saw them off before sawing off the intermediate common bars. | 10-27-2011 |
20120018858 | METHOD OF ASSEMBLING INTEGRATED CIRCUIT DEVICE - A method of assembling an integrated circuit (IC) device includes the steps of providing a lead frame or substrate panel, attaching a semiconductor die to the lead frame or substrate panel and electrically coupling the die to the lead frame or substrate panel. The method further includes encapsulating the die with a first encapsulant, and the encapsulating the first encapsulant with a second encapsulant where the second encapsulant includes a material that provides electromagnetic shielding. | 01-26-2012 |
20120326288 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICE - A method of assembling a semiconductor device includes providing a conductive lead frame panel and selectively half-etching a top side of the lead frame panel to provide a pin pads. A flip chip die is attached and electrically connected to the pin pads and then the lead frame panel and die are encapsulated with molding compound. A second selective half etching step is performed on a backside of the lead frame panel to form a plurality of separate input/output pins. The side walls of each input/output pin include arcuate surfaces in cross-section. | 12-27-2012 |
20150028468 | NON-LEADED TYPE SEMICONDUCTOR PACKAGE AND METHOD OF ASSEMBLING SAME - A no-lead type semiconductor package has a mold cap that forms a mold body. The corners of the mold body are reinforced with mold columns such that the corners have rounded protrusions and do not form 90° angles. The mold columns prevent the corner pads from peeling. | 01-29-2015 |