Patent application number | Description | Published |
20100157475 | STEPPED MAIN POLE FOR PERPENDICULAR WRITE HEADS IN HARD DISK DRIVES AND METHOD OF MAKING SAME - A stepped main pole for a perpendicular write head and methods of making the stepped main pole. The stepped main pole has a main pole tip and a base portion. The main pole tip has a surface that forms part of the ABS and a first thickness. The base portion extends from the main pole tip and has a thickness that varies from the first thickness to a second thickness to form a slanted surface with an apex angle adjacent the main pole tip. By placing the base portion away from the ABS and providing a thickness that increases in a direction away from the ABS, the stepped pole can provide the necessary magnetic flux for writing, while avoiding undesired leakage and fringing. To form embodiments of the stepped main pole of the invention, a fluorine-based reactive ion etch (RIE) may be used. By using an RIE to define the stepped main pole, the apex angle can be better controlled and tight edge control can be achieved. | 06-24-2010 |
20110075295 | SLANTED BUMP DESIGN FOR MAGNETIC SHIELDS IN PERPENDICULAR WRITE HEADS AND METHOD OF MAKING SAME - Embodiments provide a slanted bump magnetic shield in a perpendicular write head and a method of making the shield. The slanted bump magnetic shield provides a small throat height to maximize magnetic flux for writing to a magnetic media such as a magnetic storage disk in a hard disk drive, while avoiding saturation. An etch process is used to form a taper in non-magnetic gap material. The magnetic shield is then deposited on the taper, forming the slanted bump of the shield. The etch process may be a multiple etch process to provide better edge and thickness control when forming the taper. | 03-31-2011 |
20110134569 | PMR WRITER AND METHOD OF FABRICATION - Methods for fabrication of tapered magnetic poles with a non-magnetic front bump layer. A magnetic pole may have a plurality of tapered surfaces at or near and air bearing surface (ABS), wherein a thickness of the write pole increases in a direction away from the ABS. A non-magnetic front bump layer may be formed on one or more of the tapered surfaces of the magnetic pole at a distance from the ABS. The front bump layer may increase the separation distance between a shield layer and the magnetic pole near the tapered surface, thereby improving the performance of the write head. | 06-09-2011 |
20140272120 | METHOD FOR PRODUCING A SMOOTH RU SIDE GAP OF A DAMASCENE WRITER POLE - The present invention generally relates to a method for forming a smooth gap of a damascene write pole. An opening having a side wall with a first angle with respect to vertical is formed in a fill layer, and a first non-magnetic layer is deposited into the opening by ion beam deposition. The ion beam is delivered to the side wall at a second angle with respect to vertical. The ratio of the first angle to the second angle ranges from about 250 to about 3.5. | 09-18-2014 |
Patent application number | Description | Published |
20140157017 | POWER MANAGEMENT OF COMMUNICATION DEVICES - In some embodiments, a method includes processing, at a communication device, a packet received via a communication media. The method also includes reducing, while the packet is being processed, power to at least one component in the communication device, in response to a condition associated with the processing of the packet being satisfied. The method includes restoring power to the at least one component prior to receiving an entirety of the packet at the communication device. | 06-05-2014 |
20140301259 | DYNAMIC VOLTAGE AND FREQUENCY SCALING IN WIRELESS MODEMS - Methods and apparatuses are described in which dynamic voltage and frequency scaling may be used to save power when processing packets in a wireless communications device. In some cases, inframe detection may allow the device to determine whether to transition from a first (e.g., lower) voltage level to a second (e.g., higher) voltage level to process one or more packets of a received frame. For some packet types the first voltage level may be maintained. In other cases, the device may determine a bandwidth to use from among multiple bandwidths supported by the device. The bandwidth may be determined based on channel conditions. A voltage level may be identified that corresponds to the determined bandwidth and a processing voltage may be scaled to the identified voltage level. The device may be configured to operate in wireless local area network (WLAN) and/or in a cellular network (e.g., LTE). | 10-09-2014 |
20150304951 | POWER MANAGEMENT OF COMMUNICATION DEVICES - A communication device receives at least a portion of a packet. Power is reduced to a subset of components of a communication device. The subset of components for which power is reduced is determined based, at least in part, on a length of the packet. The power is reduced for a time period based, at least in part, on the length of the packet. | 10-22-2015 |
Patent application number | Description | Published |
20100106893 | PAGE BUFFER PROGRAM COMMAND AND METHODS TO REPROGRAM PAGES WITHOUT RE-INPUTTING DATA TO A MEMORY DEVICE - A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place. | 04-29-2010 |
20110141788 | PAGE REGISTER OUTSIDE ARRAY AND SENSE AMPLIFIER INTERFACE - A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits. | 06-16-2011 |
20110141832 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 06-16-2011 |
20120236663 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 09-20-2012 |
20120243349 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 09-27-2012 |