Patent application number | Description | Published |
20090297019 | METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA - Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium. | 12-03-2009 |
20120141013 | REGION BASED VIRTUAL FOURIER FILTER - The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima. | 06-07-2012 |
20130064442 | Determining Design Coordinates for Wafer Defects - Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects. | 03-14-2013 |
20150154746 | Methods and Systems for Utilizing Design Data in Combination with Inspection Data - Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium. | 06-04-2015 |
Patent application number | Description | Published |
20130011647 | Reduced-Voc and Non-Voc Blowing Agents for Making Expanded and Extruded Thermoplastic Foams - A blowing agent blend for making thermoplastic polymer foams includes methyl formate. The blowing agent blend can further comprise at least one co-blowing agent. The co-blowing agent is either a physical co-blowing agent (e.g. an inorganic agent, a hydrocarbon, a halogenated hydrocarbon, a hydrocarbon with polar, functional group(s), water or any combination thereof), or a chemical co-blowing agent, or combinations thereof. The thermoplastic polymer foam can be an alkenyl aromatic polymer foam, e.g. a polystyrene foam. The blowing agent blend includes methyl formate and one or more co-blowing agents. The methyl formate-based blowing agent blends produce dimensionally stable foams that have improved resistance to flame spread. A process for the preparation of such foams is also provided. | 01-10-2013 |
20130011648 | Reduced-Voc and Non-Voc Blowing Agents for Making Expanded and Extruded Thermoplastic Foams - A blowing agent blend for making thermoplastic polymer foams includes methyl formate. The blowing agent blend can further comprise at least one co-blowing agent. The co-blowing agent is either a physical co-blowing agent (e.g. an inorganic agent, a hydrocarbon, a halogenated hydrocarbon, a hydrocarbon with polar, functional group(s), water or any combination thereof), or a chemical co-blowing agent, or combinations thereof. The thermoplastic polymer foam can be an alkenyl aromatic polymer foam, e.g. a polystyrene foam. The blowing agent blend includes methyl formate and one or more co-blowing agents. The methyl formate-based blowing agent blends produce dimensionally stable foams that have improved resistance to flame spread. A process for the preparation of such foams is also provided. | 01-10-2013 |
20140187658 | Reduced-VOC and Non-VOC Blowing Agents for Making Expanded and Extruded Thermoplastic Foams - Process for producing a thermoplastic polymer foam article includes preparing an expandable polymeric formulation comprising a thermoplastic polymer and a blowing agent blend, forming the formulation into an expandable bead, and expanding the expandable bead to form a thermoplastic polymer foam article. The blowing agent blend includes methyl formate, hydrocarbon, and either carbon dioxide or 1,1,1,2-tetrafluoroethane (HFC-134a). The blowing agent blend has a higher effective volatility than that of methyl formate alone. A thermoplastic polymer foam article prepared by a process is also provided. | 07-03-2014 |
Patent application number | Description | Published |
20100080365 | OFFLINE VOICEMAIL - A method for accessing offline voicemail messages within a mobile messaging application may be provided. First, a voice mail message may be received and the voicemail message may be transcribed to text. Next, the voicemail message and the text transcription may be stored. The recipient may then be presented with a list of voicemail messages and the voicemail message may be retrieved in response to the recipient. The recipient may read or listen to the voicemail message or both. The recipient may also annotate the voicemail message. | 04-01-2010 |
20100082759 | COMMUNICATIONS GROUPED AS CONVERSATIONS - Described are embodiments for displaying groups of communications, such as messages, as a conversation. Conversations are groups of communications that can be traced back as related to an original communication. The embodiments allow a user to select a conversation mode for displaying communications, e.g., messages, as conversations. In response to the user's selection, embodiments provide for displaying a graphical element associated with a conversation. The graphical element can be selected to display the messages associated with the conversation. Additionally, embodiments provide for selecting a conversation and applying actions to the conversation, resulting in the application of the action to the messages that are associated with the conversation. | 04-01-2010 |
20100121922 | AUTO-RESOLVE RECIPIENTS CACHE - In embodiments, mobile devices request and utilize recipient caches. Recipient caches store information regarding previous recipients of communications. The information on recipients includes when the recipient was last contacted and the frequency with which a recipient is contacted. In embodiments, a mobile device requests a recipient cache from a server. When a user types a string of text, the mobile device then uses the recipient cache as well as the contacts and emails on the mobile device and resolves a recipient list. In other embodiments, a recipient cache on a server is updated when a mobile device sends a message with new recipient information. In another embodiment, a server resolves conflicting messages by using recipient information | 05-13-2010 |
20120150983 | AUTO-RESOLVE RECIPIENTS CACHE - In embodiments, mobile devices request and utilize recipient caches. Recipient caches store information regarding previous recipients of communications. The information on recipients includes when the recipient was last contacted and the frequency with which a recipient is contacted. In embodiments, a mobile device requests a recipient cache from a server. When a user types a string of text, the mobile device then uses the recipient cache as well as the contacts and emails on the mobile device and resolves a recipient list. In other embodiments, a recipient cache on a server is updated when a mobile device sends a message with new recipient information. In another embodiment, a server resolves conflicting messages by using recipient information | 06-14-2012 |
20130035075 | OFFLINE VOICEMAIL - A method for accessing offline voicemail messages within a mobile messaging application may be provided. First, a voice mail message may be received and the voicemail message may be transcribed to text. Next, the voicemail message and the text transcription may be stored. The recipient may then be presented with a list of voicemail messages and the voicemail message may be retrieved in response to the recipient. The recipient may read or listen to the voicemail message or both. The recipient may also annotate the voicemail message. | 02-07-2013 |
20140169538 | OFFLINE VOICEMAIL - A method for accessing offline voicemail messages within a mobile messaging application may be provided. First, a voice mail message may be received and the voicemail message may be transcribed to text. Next, the voicemail message and the text transcription may be stored. The recipient may then be presented with a list of voicemail messages and the voicemail message may be retrieved in response to the recipient. The recipient may read or listen to the voicemail message or both. The recipient may also annotate the voicemail message. | 06-19-2014 |
20140208229 | COMMUNICATIONS GROUPED AS CONVERSATIONS - Described are embodiments for displaying groups of communications, such as messages, as a conversation. Conversations are groups of communications that can be traced back as related to an original communication. The embodiments allow a user to select a conversation mode for displaying communications, e.g., messages, as conversations. In response to the user's selection, embodiments provide for displaying a graphical element associated with a conversation. The graphical element can be selected to display the messages associated with the conversation. Additionally, embodiments provide for selecting a conversation and applying actions to the conversation, resulting in the application of the action to the messages that are associated with the conversation. | 07-24-2014 |
20150065096 | OFFLINE VOICEMAIL - A method for accessing offline voicemail messages within a mobile messaging application may be provided. First, a voice mail message may be received and the voicemail message may be transcribed to text. Next, the voicemail message and the text transcription may be stored. The recipient may then be presented with a list of voicemail messages and the voicemail message may be retrieved in response to the recipient. The recipient may read or listen to the voicemail message or both. The recipient may also annotate the voicemail message. | 03-05-2015 |
Patent application number | Description | Published |
20080245658 | METHOD OF FORMING HfSiN METAL FOR n-FET APPLICATIONS - A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/ interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN. | 10-09-2008 |
20080293259 | METHOD OF FORMING METAL/HIGH-k GATE STACKS WITH HIGH MOBILITY - The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×10 | 11-27-2008 |
20080299730 | METAL OXYNITRIDE AS A pFET MATERIAL - A compound metal comprising MO | 12-04-2008 |
20100015790 | TiC AS A THERMALLY STABLE p-METAL CARBIDE ON HIGH k SiO2 GATE STACKS - A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device. | 01-21-2010 |
20100044805 | METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS - A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer. | 02-25-2010 |
20110247946 | Dual FET Sensor for Sensing Biomolecules & Charged Ions in an Electrolyte - A sensor for biomolecules or charged ions includes a substrate; a first node, a second node, and a third node located in the substrate; a gate dielectric located over the substrate, the first node, the second node, and the third node; a first field effect transistor (FET), the first FET comprising a control gate located on the gate dielectric, and the first node and the second node; and a second FET, the second FET comprising a sensing surface located on the gate dielectric, and the second node and the third node, wherein the sensing surface is configured to specifically bind the biomolecules or charged ions that are to be detected. | 10-13-2011 |
20110279125 | FET Nanopore Sensor - A method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore. | 11-17-2011 |
20120298531 | Dual FET Sensor for Sensing Biomolecules & Charged Ions in an Electrolyte - A method for operating a sensor for biomolecules or charged ions, the sensor comprising a first field effect transistor (FET) and a second FET, wherein the first FET and the second FET comprise a shared node includes placing an electrolyte containing the biomolecules or charged ions on a sensing surface of the sensor, the electrolyte comprising a gate of the second FET; applying an inversion voltage to a gate of the first FET; making a first electrical connection to an unshared node of the first FET; making a second electrical connection to unshared node of the second FET; determining a change in a drain current flowing between the unshared node of the first FET and the unshared node of the second FET; and determining an amount of biomolecules or charged ions contained in the electrolyte based on the determined change in the drain current. | 11-29-2012 |
20140027871 | CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS - A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor. | 01-30-2014 |
20140030838 | CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS - A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor. | 01-30-2014 |
20140132275 | DETERMINATION OF ISOELECTRIC POINTS OF BIOMOLECULES USING CAPACITIVE SENSORS - A mechanism is provided for determining an isoelectric point of a molecule. A first group of capacitance versus voltage curves of a capacitor is measured. The capacitor includes a substrate, dielectric layer, and conductive solution. The first group of curves is measured for pH values of the solution without the molecule bound to a functionalized material on the dielectric layer of the capacitor. A second group of capacitance versus voltage curves of the capacitor is measured when the molecule is present in the solution, where the molecule is bound to the functionalized material of the dielectric layer of the capacitor. A shift is determined in the second group of curves from the first group of curves at each pH value. The isoelectric point of the molecule is determined by extrapolating a pH value corresponding to a shift voltage being zero, when the shift is compared to the pH values. | 05-15-2014 |
20140132276 | DETERMINATION OF ISOELECTRIC POINTS OF BIOMOLECULES USING CAPACITIVE SENSORS - A mechanism is provided for determining an isoelectric point of a molecule. A first group of capacitance versus voltage curves of a capacitor is measured. The capacitor includes a substrate, dielectric layer, and conductive solution. The first group of curves is measured for pH values of the solution without the molecule bound to a functionalized material on the dielectric layer of the capacitor. A second group of capacitance versus voltage curves of the capacitor is measured when the molecule is present in the solution, where the molecule is bound to the functionalized material of the dielectric layer of the capacitor. A shift is determined in the second group of curves from the first group of curves at each pH value. The isoelectric point of the molecule is determined by extrapolating a pH value corresponding to a shift voltage being zero, when the shift is compared to the pH values. | 05-15-2014 |
20140175522 | Field Effect Transistor-Based Bio Sensor - An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus. | 06-26-2014 |
20140179047 | Field Effect Transistor-Based Bio-Sensor - An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus. | 06-26-2014 |
20140203332 | SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY - Non-planar semiconductor FET based sensors are provided that have an enhanced sensing area to volume ratio which results in faster response times than existing planar FET based sensors. The FET based sensors of the present disclosure include a V-shaped gate dielectric portion located in a V-shaped opening formed in a semiconductor substrate. In some embodiments, the FET based sensors of the present disclosure also include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of the V-shaped opening. In other embodiments, the FET based sensors include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of a gate dielectric material portion that is present on an uppermost surface of the semiconductor substrate. | 07-24-2014 |
20140327446 | FET Nanopore Sensor - A method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore. | 11-06-2014 |
20140367748 | EXTENDED GATE SENSOR FOR pH SENSING - A sensing device includes a substrate having a source region and a drain region formed therein. A gate structure is formed over the substrate and includes a gate dielectric and a gate conductor. The gate conductor is formed on the gate dielectric and disposed between the source region and the drain region. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. A gate extension is formed in contact with or as part of the gate conductor and including a conductive material covering one or more surfaces of the well. | 12-18-2014 |
20140370636 | EXTENDED GATE SENSOR FOR pH SENSING - A sensing device includes a substrate having a source region and a drain region formed therein. A gate structure is formed over the substrate and includes a gate dielectric and a gate conductor. The gate conductor is formed on the gate dielectric and disposed between the source region and the drain region. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. A gate extension is formed in contact with or as part of the gate conductor and including a conductive material covering one or more surfaces of the well. | 12-18-2014 |
20150137191 | FIELD EFFECT TRANSISTOR-BASED BIO-SENSOR - An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus. | 05-21-2015 |
20150253438 | CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS - A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor. | 09-10-2015 |
20150295119 | CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS - A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor. | 10-15-2015 |
Patent application number | Description | Published |
20110033952 | Sensor for Biomolecules - A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies. | 02-10-2011 |
20110115027 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 05-19-2011 |
20110163812 | ULTRA LOW-POWER CMOS BASED BIO-SENSOR CIRCUIT - An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material. | 07-07-2011 |
20120001614 | ULTRA LOW-POWER CMOS BASED BIO-SENSOR CIRCUIT - An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material. | 01-05-2012 |
20120282596 | Sensor for Biomolecules - A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current. | 11-08-2012 |
20130005156 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 01-03-2013 |
20140299922 | HIGH-K METAL GATE DEVICE STRUCTURE FOR HUMAN BLOOD GAS SENSING - A device structure for detecting partial pressure of oxygen in blood includes a semiconductor substrate including a source region and a drain region. A multi-layer gate structure is formed on the semiconductor substrate. The multi-layer gate structure includes an oxide layer formed over the semiconductor substrate, a high-k layer formed over the oxide layer, a metal gate layer formed over the high-k layer, and a polysilicon layer formed over the metal gate layer. A receiving area holds a blood sample in contact with the multi-layer gate structure. The high-k layer is exposed to contact the blood sample in the receiving area. | 10-09-2014 |
20140300340 | HIGH-K METAL GATE DEVICE STRUCTURE FOR HUMAN BLOOD GAS SENSING - A device structure for detecting partial pressure of oxygen in blood includes a semiconductor substrate including a source region and a drain region. A multi-layer gate structure is formed on the semiconductor substrate. The multi-layer gate structure includes an oxide layer formed over the semiconductor substrate, a high-k layer formed over the oxide layer, a metal gate layer formed over the high-k layer, and a polysilicon layer formed over the metal gate layer. A receiving area holds a blood sample in contact with the multi-layer gate structure. The high-k layer is exposed to contact the blood sample in the receiving area. | 10-09-2014 |
20150014752 | THIN BODY FET NANOPORE SENSOR FOR SENSING AND SCREENING BIOMOLECULES - A thin body field effect transistor (FET) nanopore sensor includes a silicon on insulator (SOI) structure having an annular shape and comprising a source, a drain and a thin body channel interposed therebetween. A nanopore is formed in a central opening of the SOI structure. A gate dielectric is disposed on the SOI structure insulating the SOI structure from a liquid gate within the nanopore. A back gate is formed around the SOI structure. A shallow trench isolation (STI) layer is formed between the SOI structure and the back gate. | 01-15-2015 |
20150279746 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 10-01-2015 |
20150279937 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 10-01-2015 |
20150311127 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 10-29-2015 |
20150311303 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 10-29-2015 |