Patent application number | Description | Published |
20080218529 | Image Creating Device, Load Display Method, Recording Medium, And Program - An operation input reception unit ( | 09-11-2008 |
20080219075 | Control of inputs to a memory device - A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. | 09-11-2008 |
20080222483 | Method, system, and apparatus for distributed decoding during prolonged refresh - Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode. | 09-11-2008 |
20080282098 | Semiconductor memory device and error correction method therof - A semiconductor memory device comprising: a memory array having a data area and a check code area; refresh control means which controls a refresh operation in a data holding state; operation means which executes an encoding operation for generating the check code using a bit string in the data area, and executes a decoding operation for performing the error detection/correction of the data using the check code; encode control means for controlling an encode process in which in a change to the data holding state, a first and second code are written in the check code area; and decode control means for controlling a decode process in which at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively. | 11-13-2008 |
20080298152 | POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed. | 12-04-2008 |
20090049455 | COMMAND INTERFACE SYSTEMS AND METHODS - Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed. | 02-19-2009 |
20090116328 | POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period. | 05-07-2009 |
20090193301 | Semiconductor memory device and refresh period controlling method - Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors. | 07-30-2009 |
20090249148 | ERROR-CORRECTION FORCED MODE WITH M-SEQUENCE - Improved apparatus, systems and methods, such as those for testing an error correction code (ECC) encoder/decoder for solid-state memory devices, are provided. In one or more embodiments, the improved systems and methods deliberately inject errors into memory storage areas of memory devices to test the operation of the ECC encoder/decoder. | 10-01-2009 |
20090297868 | Method for Forming Self-Assembled Monolayer Film, and Structural Body and Field-Effect Transistor Having Same - A method for forming a self-organized monomolecular film, including at least: dissolving an alkylsilane compound having at least an alkoxysilane group or a chlorosilane group at one end of a molecule in an organic solvent having a dielectric constant of 3.0 or more to 6.0 or less to obtain a solution; subsequently coating the solution on a base material or immersing the base material into the solution; and subsequently drying the solution located on the base material. | 12-03-2009 |
20100135065 | POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period. | 06-03-2010 |
20100289024 | Insulating Thin Film, Formation Solution For Insulating Thin Film, Field-Effect Transistor, Method For Manufacturing The Same And Image Display Unit - One embodiment of the present invention is an insulating thin film having a polymer compound, a metallic atom bonded to the polymer compound through an oxide atom and selected from a group 4 element, a group 5 element, a group 6 element, a group 13 element, zinc or tin, and an organic molecule bonded to the metallic atom through the oxide atom or a nitrogen atom. | 11-18-2010 |
20110148469 | STACKED DEVICE DETECTION AND IDENTIFICATION - Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths. | 06-23-2011 |
20110194326 | MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS - Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node. | 08-11-2011 |
20110205813 | POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period. | 08-25-2011 |
20110299353 | POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed. | 12-08-2011 |
20110302328 | COMMAND INTERFACE SYSTEMS AND METHODS - Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed. | 12-08-2011 |
20120036411 | METHOD, SYSTEM, AND APPARATUS FOR DISTRIBUTED DECODING DURING PROLONGED REFRESH - Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode. | 02-09-2012 |
20120131419 | MEMORY APPARATUS AND METHOD USING ERASURE ERROR CORRECTION TO REDUCE POWER CONSUMPTION - Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed. | 05-24-2012 |
20120188831 | POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described. | 07-26-2012 |
20120324298 | MEMORY DEVICE REPAIR APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed. | 12-20-2012 |
20130077417 | CONTROL OF INPUTS TO A MEMORY DEVICE - A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. | 03-28-2013 |
20130082001 | Fresh Water Generating Apparatus and Fresh Water Generating Method - An object of the present invention is to provide a fresh water generating apparatus that is capable of efficiently producing fresh water according to an intended use, while utilizing wastewater. Provided is a fresh water generating apparatus equipped with a seawater-treating reverse osmosis membrane device that produces fresh water from seawater by a reverse osmosis membrane, which includes: a mixing section that mixes wastewater as dilution water with a portion of seawater to be subjected to membrane treatment to produce mixed water; a first seawater-treating reverse osmosis membrane device that acts as the seawater-treating reverse osmosis membrane device to filter the mixed water; and a second seawater-treating reverse osmosis membrane device that acts as the seawater-treating reverse osmosis membrane device to filter the remaining portion of the seawater to be subjected to membrane treatment, in an unmixed state with the dilution water. | 04-04-2013 |
20130206697 | Fresh Water Generating Apparatus and Fresh Water Generating Method - An object is to provide a fresh water generating apparatus that is capable of efficiently and stably producing fresh water. Provided is a fresh water generating apparatus equipped with a seawater-treating reverse osmosis membrane device that produces fresh water from seawater by a reverse osmosis membrane, including a mixing section that mixes wastewater as dilution water with seawater to produce mixed water, and a first seawater-treating reverse osmosis membrane device that acts as the seawater-treating reverse osmosis membrane device to filter the mixed water, in which the apparatus is configured so that used water that is wastewater resulting from the use of the produced fresh water as service water is mixed as dilution water with seawater at the mixing section. | 08-15-2013 |
20140078849 | CONTROL OF INPUTS TO A MEMORY DEVICE - A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. | 03-20-2014 |