Yurzola
Damian Yurzola, Santa Clara, CA US
Patent application number | Description | Published |
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20120030412 | Systems and Methods for Implementing a Programming Sequence to Enhance Die Interleave - Systems and methods for sequentially writing data to a memory device such as a universal serial bus (USB) memory device are disclosed. A system controller of a memory device including a first die and a second die, each of the first die and the second die including a plurality of pages, writes a first portion of a set of data to a lower page of a second die. The system controller then writes a second portion of the set of data to an upper page of the second die after writing the first portion of the set of data to the lower page of the second die. | 02-02-2012 |
Damian P. Yurzola, Santa Clara, CA US
Patent application number | Description | Published |
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20110161559 | PHYSICAL COMPRESSION OF DATA WITH FLAT OR SYSTEMATIC PATTERN - Systems and methods are disclosed to improve the performance of a memory system by freeing up physical memory areas that correspond to logical block address ranges that have repeated data patterns. A controller detects data patterns in incoming data. When a data pattern is detected, the data is not written to non-volatile storage area. Rather, the logical block address range of the data is marked in a data structure as having pattern data. The pattern may also be recorded in the data structure as a pattern descriptor. Because the data having the data pattern is not written to the non-volatile storage area, the freed up corresponding physical memory area may be utilized by the memory system for other purposes, thereby improving the overall performance and endurance of the memory system. | 06-30-2011 |
20120331282 | APPARATUS AND METHODS FOR PEAK POWER MANAGEMENT IN MEMORY SYSTEMS - Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system. | 12-27-2012 |
20140237167 | Apparatus and Methods for Peak Power Management in Memory Systems - Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system. | 08-21-2014 |
Damian Pablo Yurzola, Santa Clara, CA US
Patent application number | Description | Published |
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20110154158 | SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE - A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion. | 06-23-2011 |
20110154160 | SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE - A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array. | 06-23-2011 |
20140157087 | Bad Column Handling in Flash Memory - In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns. | 06-05-2014 |