Patent application number | Description | Published |
20110102047 | Radio Frequency (RF) Power Detector Suitable for Use in Automatic Gain Control (AGC) - In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators. | 05-05-2011 |
20120250789 | GENERATING A MODULATED SIGNAL FOR A TRANSMITTER - A technique includes generating an angle modulated square wave signal and progressively filtering the angle modulated square wave signal in a transmitter using a plurality of low pass filters to produce a modulated sinusoidal signal to drive an antenna. The technique includes programming the transmitter to tune a corner frequency of the filtering to a frequency within a range of frequencies selectable using the programming, based on a carrier frequency associated with the modulated sinusoidal signal. | 10-04-2012 |
20120252383 | TRANSMITTER - A transmitter is adapted to be programmed to select an amplifier operating class for the transmitter out of a plurality of amplifier operating classes. The transmitter is also adapted to operate according to the selected amplifier operating class to communicate a signal to an antenna. | 10-04-2012 |
20120299623 | RADIO FREQUENCY (RF) POWER DETECTOR SUITABLE FOR USE IN AUTOMATIC GAIN CONTROL (AGC) - In one form, a power converter for a power detector or the like includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. | 11-29-2012 |
20130002357 | Providing Automatic Power Control For A Power Amplifier - A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level. | 01-03-2013 |
20140176201 | TIME-INTERLEAVED DIGITAL-TO-TIME CONVERTER - A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage. | 06-26-2014 |
20140307759 | Isolated Serializer-Deserializer - A first integrated circuit die receives input data from a plurality of input channels and combines the input data from the plurality of input channels into combined data. The first integrated circuit die transmits the combined data across an isolation communication channel. A second integrated circuit die that is coupled to the isolation communication channel decodes the transmitted combined data and supplies the decoded transmitted combined data to respective output channels corresponding to the input channels. | 10-16-2014 |
20150048895 | ACCURATE FREQUENCY CONTROL USING A MEMS-BASED OSCILLATOR - A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference. | 02-19-2015 |