| Patent application number | Description | Published |
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| 20090001615 | SEMICONDUCTOR TEST STRUCTURES - Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds. | 01-01-2009 |
| 20090004879 | TEST STRUCTURE FORMATION IN SEMICONDUCTOR PROCESSING - Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices. | 01-01-2009 |
| 20090004880 | MASK REUSE IN SEMICONDUCTOR PROCESSING - A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers. | 01-01-2009 |
| 20090087963 | METHOD FOR REDUCING PILLAR STRUCTURE DIMENSIONS OF A SEMICONDUCTOR DEVICE - A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist. | 04-02-2009 |
| 20090230571 | MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE - A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described. | 09-17-2009 |
| 20090269932 | Method for fabricating self-aligned complimentary pillar structures and wiring - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask. | 10-29-2009 |
| 20090321789 | Triangle two dimensional complementary patterning of pillars - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape. | 12-31-2009 |
| 20100012032 | Apparatus for high-rate chemical vapor deposition - An apparatus for high-rate chemical vapor (CVD) deposition of semiconductor films comprises a reaction chamber for receiving therein a substrate and a film forming gas, a gas inlet for introducing the film forming gas into the reaction chamber, an incidence window in the reaction chamber for transmission of a laser sheet into the reaction chamber, a laser disposed outside the reaction chamber for generating the laser sheet and an antenna disposed outside the reaction chamber for generating a plasma therein. The film forming gas in the chamber is excited and decomposed by the laser sheet, which passes in parallel with the substrate along a plane spaced apart therefrom, and concurrent ionization effected by the antenna, thereby forming a dense semiconductor film on the substrate at high rate. | 01-21-2010 |
| 20100081260 | Method for forming a semiconductor film - An apparatus for high-rate chemical vapor (CVD) deposition of semiconductor films comprises a reaction chamber for receiving therein a substrate and a film forming gas, a gas inlet for introducing the film forming gas into the reaction chamber, an incidence window in the reaction chamber for transmission of a laser sheet into the reaction chamber, a laser disposed outside the reaction chamber for generating the laser sheet and an antenna disposed outside the reaction chamber for generating a plasma therein. The film forming gas in the chamber is excited and decomposed by the laser sheet, which passes in parallel with the substrate along a plane spaced apart therefrom, and concurrent ionization effected by the antenna, thereby forming a dense semiconductor film on the substrate at high rate. | 04-01-2010 |
| 20100086875 | Method of making sub-resolution pillar structures using undercutting technique - A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask. | 04-08-2010 |
| 20100105210 | Method of making pillars using photoresist spacer mask - A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask. | 04-29-2010 |
| 20100167502 | Nanoimprint enhanced resist spacer patterning method - A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask. | 07-01-2010 |
| 20100167520 | Resist feature and removable spacer pitch doubling patterning method for pillar structures - A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one layer using the first feature, the filler feature and the second feature as a mask. | 07-01-2010 |
| 20100180935 | Multiple band gapped cadmium telluride photovoltaic devices and process for making the same - A heterojunction photovoltaic device for the production of electrical energy in response to the incident light includes an optically transparent substrate, a front contact formed of an transparent conductive oxide for collecting light generated charge carriers, an n-type window layer formed of cadmium sulfide or zinc sulfide, a p-type absorber structure disposed on the window layer, thereby forming a rectification junction therebetween, and a back contact comprising at least one metal layer. The p-type absorber structure has a plurality of p-type absorber layers in contiguous contact. Each absorber layer contains cadmium as a principal constituent and has a different composition and a different band gap energy. The first absorber layer is in contiguous contact with the n-type window layer. The band gap energy progressively decreases from the first absorber layer to the last absorber layer in the p-type absorber structure. | 07-22-2010 |
| 20100184249 | Continuous deposition process and apparatus for manufacturing cadmium telluride photovoltaic devices - A continuous deposition process and apparatus for depositing semiconductor layers containing cadmium, tellurium or sulfur as a principal constituent on transparent substrates to form photovoltaic devices as the substrates are continuously conveyed through the deposition apparatus is described. The film deposition process for a photovoltaic device having an n-type window layer and three p-type absorber layers in contiguous contact is carried out by a modular continuous deposition apparatus which has a plurality of processing stations connected in series for depositing successive layers of semiconductor films onto continuously conveying substrates. The fabrication starts by providing an optically transparent substrate coated with a transparent conductive oxide layer, onto which an n-type window layer formed of CdS or CdZnS is sputter deposited. After the window layer is deposited, a first absorber layer is deposited thereon by sputter deposition. Thereafter, a second absorber layer formed of CdTe is deposited onto the first absorber layer by a novel vapor deposition process in which the CdTe film forming vapor is generated by sublimation of a CdTe source material. After the second absorber layer is deposited, a third absorber layer formed of CdHgTe is deposited thereon by sputter deposition. The substrates are continuously conveyed through the modular continuous deposition apparatus as successive layers of semiconductor films are deposited thereon. | 07-22-2010 |
| 20100193916 | METHODS FOR INCREASED ARRAY FEATURE DENSITY - The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays. | 08-05-2010 |
| 20100243602 | IMAGING POST STRUCTURES USING X AND Y DIPOLE OPTICS AND A SINGLE MASK - A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A | 09-30-2010 |
| 20100301449 | METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY - The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed. | 12-02-2010 |
