Patent application number | Description | Published |
20080197461 | Apparatus for wire bonding and integrated circuit chip package - An apparatus for wire bonding and a capillary tool thereof are provided. An exemplary embodiment of a capillary tool capable of a wire bonding comprises a body having a first internal channel of a first diameter for accommodating a flow of a conductive wire. A compressible head is connected to the body, having a second internal channel of a second diameter for accommodating the flow of the conductive wire, wherein the first diameter is fixed and the second diameter is variable, the second diameter is not more than the first diameter and a diameter the conductive wire flowed through the compressible head is adjustable. An integrated circuit (IC) package is also provided. | 08-21-2008 |
20080233745 | Interconnect Structures for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 09-25-2008 |
20080233765 | Method for enhancing adhesion between layers - A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging. | 09-25-2008 |
20080251928 | Carbonization of metal caps - An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring. | 10-16-2008 |
20080280449 | SELF-ALIGNED DIELECTRIC CAP - A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little or no dielectric cap is formed over the non-copper region of the substrate. | 11-13-2008 |
20090014877 | Selective Formation of Boron-Containing Metal Cap Pre-layer - An interconnect structure with improved reliability is provided. The interconnect structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metallic wiring in the dielectric layer; a pre-layer over the metallic wiring, wherein the pre-layer contains boron; and a metal cap over the pre-layer, wherein the metal cap contains tungsten, and wherein the pre-layer and the metal cap are formed of different materials. | 01-15-2009 |
20090152722 | Synergy Effect of Alloying Materials in Interconnect Structures - A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line comprises an alloying material; and forming an etch stop layer on the copper line. | 06-18-2009 |
20090275195 | Interconnect Structure Having a Silicide/Germanide Cap Layer - An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide. | 11-05-2009 |
20100059893 | Synergy Effect of Alloying Materials in Interconnect Structures - A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line. | 03-11-2010 |
20100065969 | Integrated circuit device - An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer. | 03-18-2010 |
20100090343 | Interconnect Structure for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 04-15-2010 |
20100213518 | Impurity Doped UV Protection Layer - An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples. | 08-26-2010 |
20110027991 | Interconnect Structure for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 02-03-2011 |
20110081758 | Semiconductor device including I/O oxide nitrided core oxide on substrate, and method of manufacture - A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide. | 04-07-2011 |
20130102148 | Interconnect Structure for Semiconductor Devices - A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium. | 04-25-2013 |
20150017800 | Interconnect Structure for Semiconductor Devices - A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium. | 01-15-2015 |