Patent application number | Description | Published |
20130088925 | LAYOUT OF MEMORY CELLS - A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region. | 04-11-2013 |
20130088926 | TRACKING MECHANISMS - A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro. | 04-11-2013 |
20140032871 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell. | 01-30-2014 |
20140282318 | TIMING DELAY CHARACTERIZATION METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay. | 09-18-2014 |
20140282319 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted. | 09-18-2014 |
20150029797 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line. | 01-29-2015 |
20150071016 | TRACKING MECHANISMS - A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated. | 03-12-2015 |
20150095867 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block. | 04-02-2015 |