Patent application number | Description | Published |
20090153203 | PLL CIRCUIT - A PLL comprises a current-controlled oscillator ( | 06-18-2009 |
20090262876 | PHASE COMPARATOR AND REGULATION CIRCUIT - A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits. | 10-22-2009 |
20100002822 | PHASE COMPARATOR, PHASE COMPARISON DEVICE, AND CLOCK DATA RECOVERY SYSTEM - A comparison period detecting unit ( | 01-07-2010 |
20100171533 | PLL CIRCUIT - A PLL comprises a current-controlled oscillator ( | 07-08-2010 |
20100177790 | TIMING RECOVERY CIRCUIT, COMMUNICATION NODE, NETWORK SYSTEM, AND ELECTRONIC DEVICE - A comparison period determiner ( | 07-15-2010 |
20110115531 | PLL CIRCUIT - A PLL comprises a current-controlled oscillator ( | 05-19-2011 |
20110164693 | INTERFACE CIRCUIT - An interface circuit including an LSI ( | 07-07-2011 |
20130148704 | ADAPTIVE RECEIVER SYSTEM AND ADAPTIVE TRANSCEIVER SYSTEM - A phase comparison circuit outputs a first phase comparison signal indicating whether or not an edge of an equalization signal is in a first interval between sampling timing and timing having a first predetermined phase advance, and outputs a second phase comparison signal indicating whether or not the edge of the equalization signal is in a second interval between the sampling timing and timing having a second predetermined phase delay. A determination circuit compares a predetermined comparison target pattern with output patterns of the first and second phase comparison signals corresponding to each bit of a detection data pattern. | 06-13-2013 |