Patent application number | Description | Published |
20110309426 | Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory - High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction. | 12-22-2011 |
20110309430 | Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation - High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction. | 12-22-2011 |
20120001252 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 01-05-2012 |
20120199898 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 08-09-2012 |
20130069138 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 03-21-2013 |
20130334587 | Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory - High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction. | 12-19-2013 |
20140001533 | NAND Memory Device Containing Nanodots and Method of Making Thereof | 01-02-2014 |
20140001535 | Non-Volatile Memory Structure Containing Nanodots and Continuous Metal Layer Charge Traps and Method of Making Thereof | 01-02-2014 |
20140151778 | Select Gate Formation for Nanodot Flat Cell - Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches. | 06-05-2014 |
20140175530 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 06-26-2014 |
20140346583 | INVERTED-T WORD LINE AND FORMATION FOR NON-VOLATILE STORAGE - A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines. | 11-27-2014 |
20140346584 | MEMORY DEVICE WITH CONTROL GATE OXYGEN DIFFUSION CONTROL AND METHOD OF MAKING THEREOF - An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate. | 11-27-2014 |
20150072488 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 03-12-2015 |