Patent application number | Description | Published |
20090173946 | PIXEL STRUCTURE AND ACTIVE DEVICE ARRAY SUBSTRATE - A pixel structure including an active device, a common line pattern, a protective layer, a pixel electrode, and a patterned semiconductor layer is provided. The active device is disposed on a substrate. In addition, the common line pattern is disposed on the substrate and covered with an insulation layer. The protective layer covers the active device and a part of the insulation layer. The protective layer has a contact window exposing the active device. The pixel electrode is disposed on the protective layer and electrically connected to the active device through the contact window. The patterned semiconductor layer is disposed on the insulation layer above the common line pattern. The patterned semiconductor layer is located between the common line pattern and the pixel electrode. | 07-09-2009 |
20090256986 | PIXEL STRUCTURE AND REPAIRING METHOD THEREOF - A pixel structure includes a scan line, a gate, a common line, a first dielectric layer, a channel layer, a source, a drain, a data line, a capacitance coupling electrode (CCE), a second dielectric layer and a pixel electrode. The gate, the common line and the scan line are disposed on the substrate, and the gate is electrically connected to the scan line. The common line has at least one first opening, and at least a portion of the first opening is located between the data line and the CCE. The channel layer is disposed on the first dielectric layer above the gate. The source and the drain are disposed on the channel layer. The CCE is disposed on the first dielectric layer above the common line and electrically connected to the drain. The pixel electrode is disposed on the second dielectric layer, and electrically connected to the CCE. | 10-15-2009 |
20100002164 | PIXEL STRUCTURES AND FABRICATING METHODS THEREOF - A fabricating method of a pixel structure is provided, which uses the original processes of fabricating a thin film transistor to simultaneously fabricate a reflective layer with an uneven surface. In the fabrication process of the thin film transistor, a plurality of bumps are formed under the reflective layer which is to be formed later on. The bumps and a gate of the TFT are formed simultaneously or the bumps and a semiconductor layer of the TFT are formed simultaneously. In addition, by stacking layers on the bumps, the reflective layer formed on the bumps can have good uneven shapes on the surface thereon. Therefore, the fabricating method of a pixel structure has simple processes and low manufacturing costs, and can be used for fabricating a transflective pixel structure or a reflective pixel structure. | 01-07-2010 |
20100328563 | PIXEL SET - A pixel set including two scan lines parallel to each other, a data line intersected with the scan lines, and two pixels located between the scan lines is provided. The pixels are at two sides of the data line, respectively. Each pixel includes an active device disposed adjacent to the data line, a pixel electrode, a storage capacitance electrode partially overlapped with the pixel electrode, and a drain compensating pattern including a branch. The branch is located at a side of the pixel electrode away from the data line, and has a concavity located at a side of the branch adjacent to the data line. The drain compensating pattern is connected to a drain of the active device. A portion of the drain compensating pattern is located inside the concavity. The branch is not overlapped with the drain compensating pattern at a side of the concavity away from the gate. | 12-30-2010 |
20110205460 | Liquid Crystal Display Device with Repairable Structure - The present invention discloses a liquid crystal display device with repairable structure, including a glass substrate; a wire structure formed on the glass substrate, wherein the wire structure includes one or a plurality of through holes formed therein; a dielectric layer formed on the wire structure and the glass substrate; and a plurality of pixel electrodes formed on the dielectric layer, wherein one or more gaps are formed between the plurality of pixel electrodes and the position of the gaps aligns with the position of the through holes. | 08-25-2011 |
20110254831 | SCAN DRIVE CONTROL SYSTEM AND METHOD FOR LIQUID CRYSTAL PANEL AND COMPUTER PROGRAM PRODUCT THEREOF - A scan drive control system and method for a liquid crystal panel and a computer program product thereof are provided for controlling a plurality of gate scan lines. The system includes a time controller, a gate integrated circuit (IC), and selection modules. The time controller generates a scan signal periodically and the scan signal is acquired by the gate IC. The gate IC outputs the scan signals according to a sequence of master scan control lines, and outputs an enable signal corresponding to the scan signal and an occurred period of the scan signal according to an enable circuit. Each selection module is connected to a master scan control line and a plurality of local gate scan lines. One of the selection modules acquires the scan and the enable signals, selects a target gate scan line from the local gate scan lines connected to the selection module, and outputs the scan signal. | 10-20-2011 |
20120140159 | PIXEL ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A pixel array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of active devices, a passivation layer, a common electrode, a dielectric layer, and a plurality of pixel electrodes. The substrate has a display area and a peripheral area. The scan lines and the data lines are intersected. The active devices are electrically connected to the scan lines and the data lines. The passivation layer covers the active devices. The common electrode is configured on the passivation layer and located in at least the display area. The dielectric layer covers the common electrode. The pixel electrodes are configured on the dielectric layer. Each of the pixel electrodes is electrically connected to one of the active devices. Each of the pixel electrodes has a plurality of slits. A portion of the common electrode under the slits is not shaded by the pixel electrodes. | 06-07-2012 |
20140189276 | METADATA CONTAINERS WITH INDIRECT POINTERS - A method is provided for managing a file system including data objects. The data objects, indirect pointers and source pointers are stored in containers that have addresses and include addressable units of a memory. The objects are mapped to addresses for corresponding containers. The indirect pointer in a particular container points to the address of a container in which the corresponding object is stored. The source pointer in the particular container points to the address of the container to which the object in the particular container is mapped. An object in a first container is moved to a second container. The source pointer in the first container is used to find a third container to which the object is mapped. The indirect pointer in the third container is updated to point to the second container. The source pointer in the second container is updated to point to the third container. | 07-03-2014 |
20140307505 | MEMORY DISTURB REDUCTION FOR NONVOLATILE MEMORY - Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array. | 10-16-2014 |
Patent application number | Description | Published |
20110161562 | REGION-BASED MANAGEMENT METHOD OF NON-VOLATILE MEMORY - A region-based management method of a non-volatile memory is provided. In the region-based management method, the storage space of all chips in the non-volatile memory is divided into physical regions, physical block sets, and physical page sets, and a logical space is divided into virtual regions, virtual blocks, and virtual pages. In the non-volatile memory, each physical block set is the smallest unit of space allocation and garbage collection, and each physical page set is the smallest unit of data access. The region-based management method includes a three-level address translation architecture for converting logical block addresses into physical block addresses. | 06-30-2011 |
20110161563 | BLOCK MANAGEMENT METHOD OF A NON-VOLATILE MEMORY - A block management method applicable to a non-volatile memory storage system is provided. The non-volatile memory storage system includes a plurality of chips. Each chip includes a plurality of physical blocks. The physical blocks form a plurality of physical block sets. Each logical block in a logical space corresponds to at most two physical block sets. In the block management method, when a logical block corresponds to two physical block sets filled with data and more data is to be written, a free physical block set is allocated for storing the data. Then, one of the two physical block sets corresponding to the logical block is selected according to a predetermined criterion. The valid data in the selected physical block set is copied into the free physical block set. Next, the selected physical block set is erased and collected to the pool of free physical block sets. | 06-30-2011 |
20140189286 | WEAR LEVELING WITH MARCHING STRATEGY - A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window. The method comprises, upon detection of a request to write a data object having a logical address mapped to a location outside the active window, updating the mapping so that the logical address maps to a selected location within the active window, and then allowing the write to the selected location. The method comprises maintaining access data indicating utilization of the plurality of address segments in the active window, and adding and removing address segments from the active window in response to the access data. | 07-03-2014 |
20140310447 | HALF BLOCK MANAGEMENT FOR FLASH STORAGE DEVICES - A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid. | 10-16-2014 |