Patent application number | Description | Published |
20080211106 | VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF - A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer. | 09-04-2008 |
20080251889 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the dielectric layer. | 10-16-2008 |
20120241908 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer. | 09-27-2012 |
20130171766 | Annealing Methods for Backside Illumination Image Sensor Chips - A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer. | 07-04-2013 |
20130207218 | Novel Condition Before TMAH Improved Device Performance - The present disclosure relates to a method of forming a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the method comprises forming a plurality of photodetectors within a front-side of a semiconductor substrate. An implant is performed on the back-side of the semiconductor substrate to form an implantation region having a doping concentration that is greater in the center than at the edges of the semiconductor substrate. The back-side of the workpiece is then exposed to an etchant, having an etch rate that is inversely proportional to the doping concentration, which thins the semiconductor substrate to a thickness that allows for light to pass through the back-side of the substrate to the plurality of photodetectors. By implanting the substrate prior to etching, the etching rate is made uniform over the back- side of the substrate improving total thickness variation between the photodetectors and the back-side of the substrate. | 08-15-2013 |
20130273735 | Oxidation-Free Copper Metallization Process Using In-situ Baking - A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing a plasma process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer | 10-17-2013 |
20140264707 | NOVEL CONDITION BEFORE TMAH IMPROVED DEVICE PERFORMANCE - The present disclosure relates to a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the BSI CSI has a semiconductor substrate with a front-side and a back-side. A plurality of photodetectors are located within the front-side of the semiconductor substrate. An implantation region is located within the semiconductor substrate at a position separated from the plurality of photodetectors. The implantation region is disposed below the plurality of photodetectors and has a non-uniform doping concentration along a lateral plane parallel to the back-side of the semiconductor substrate. The non-uniform doping concentration allows for the BSI CSI to achieve a small total thickness variation (TTV) between one or more photodetectors and a back-side of a thinned semiconductor substrate that provides for good device performance. | 09-18-2014 |
20150228537 | Contact Critical Dimension Control - In a method for manufacturing a semiconductor device, a dielectric layer is formed on a substrate, and a contact hole is formed from the dielectric layer to the substrate. A dielectric spacer liner is formed to cover a sidewall and a bottom of the contact hole. A portion of the dielectric spacer liner is removed to expose a portion of the substrate. A metal silicide layer is formed into the substrate through the contact hole. | 08-13-2015 |