Patent application number | Description | Published |
20100040182 | BUST-MODE CLOCK AND DATA RECOVERY CIRCUIT USING PHASE SELECTING TECHNOLOGY - A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase. | 02-18-2010 |
20100169402 | FAST FOURIER TRANSFORM PROCESSOR - An FFT processor is disclosed, which includes a first multi-pipelined MDC unit, a second multi-pipelined MDC unit and a switching network. The first multi-pipelined MDC unit and the second multi-pipelined MDC unit respectively employ a plurality of MDC circuits to change the positions of the delayers thereof in parallel way. By changing the operation time sequence of the signals in the first multi-pipelined MDC unit and the second multi-pipelined MDC unit, the first multi-pipelined MDC unit is able to directly send the operation results to the second multi-pipelined MDC unit through the switching network. | 07-01-2010 |
20100239253 | Passive Optical Network System Supporting Wireless Communication - A passive optical network (PON) system supporting wireless communication includes an optical line terminal (OLT) configured on a central office, an optical distribution network (ODN), and a plurality of optical network units (ONUs) respectively configured on user ends. The ODN is connected to the OLT and the ONUs in a one-to-many manner. The OLT sends a downstream optical signal to the ODN, and receives an upstream optical signal. The ODN circularly guides the optical signal to each ONU. Each ONU receives and reflects the downstream optical signal, processes the received downstream optical signal, receives and processes the upstream optical signal, carries an electrical signal to be uploaded into the upstream optical signal, and carries data received by a remote antenna into the upstream optical signal. Through the above architecture, the PON system supports wireless communication. | 09-23-2010 |
20100247100 | METHOD FOR RECEIVING OPTICAL ORTHOGONAL FREQUENCY-DIVISION MULTIPLEXING SIGNAL AND RECEIVER THEREOF - A method for receiving an optical orthogonal frequency-division multiplexing (OFDM) signal and a receiver thereof are applicable to an optical OFDM system. The receiving method includes the following steps. An optical signal is converted into a digital signal. A symbol boundary of the digital signal is estimated. A guard interval of the digital signal is removed according to the symbol boundary, so as to generate an electrical signal. The electrical signal is converted into a plurality of frequency domain sub-carriers in a fast Fourier transform (FFT) manner. A timing offset is estimated with pilot carriers and frequency domain sub-carriers corresponding to the same symbol period. The estimated symbol boundary is compensated with the timing offset. Each frequency domain sub-carrier includes a plurality of pilot carrier signals. Through the receiving method, the timing offset arisen from chromatic dispersion of an optical fiber is effectively estimated and adopted for compensation. | 09-30-2010 |
20100284695 | PRE-COMPENSATION METHOD FOR DELAYS CAUSED BY OPTICAL FIBER CHROMATIC DISPERSION, MULTI-SUB-CARRIER SIGNAL GENERATOR APPLYING THE METHOD, AND TRANSMITTER OF OPTICAL-OFDM SYSTEM APPLYING THE SIGNAL GENERATOR - A pre-compensation method for delays caused by optical fiber chromatic dispersion, a multi-sub-carrier signal generator applying the method, and a transmitter applying the signal generator are applicable to an optical orthogonal frequency-division multiplexing (OFDM) system. The pre-compensation method includes receiving a plurality of pre-compensation values, in which the pre-compensation values correspond to sub-carriers; and transmitting the sub-carriers after delaying the sub-carriers by time of the corresponding pre-compensation values. The delay time between the sub-carriers is estimated at a receiver end and a pre-compensation value of the transmitter is set according to the delay time. The transmitter delays the pre-compensation values respectively when transmitting the respective sub-carriers. Therefore, the respective sub-carriers are able to reach a receiver at nearly the same time, thereby achieving a purpose of pre-compensating for the delays caused by optical fiber chromatic dispersion. | 11-11-2010 |
Patent application number | Description | Published |
20140037564 | NOVEL COMPOUND HAVING SKIN-WHITENING, ANTI-OXIDIZING AND PPAR ACTIVITIES AND MEDICAL USE THEREFOR - Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPARα and PPARγ activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease. | 02-06-2014 |
20150017111 | NOVEL COMPOUND HAVING SKIN-WHITENING, ANTI-OXIDIZING AND PPAR ACTIVITIES AND MEDICAL USE THEREOF - Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPARα and PPARγ activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease. | 01-15-2015 |
20150366776 | NOVEL COMPOUND HAVING SKIN-WHITENING, ANTI-OXIDIZING AND PPAR ACTIVITIES AND MEDICAL USE THEREOF - Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPARα and PPARγ activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease. | 12-24-2015 |
Patent application number | Description | Published |
20100066404 | Reduced Power Differential Type Termination Circuit - A reduced power differential type termination circuit for use in SSTL, HSTL and other transmission line systems reduces power consumption. A differential type termination circuit may comprise first and second nodes for coupling, respectively, to first and second transmission lines; a first impedance coupled between the first transmission line and a third node; a second impedance coupled between the second transmission line and the third node; and a low direct current reference voltage generator for generating a reference voltage applied to the third node. The first and second transmission lines may transmit complimentary signals. The first and second impedances may be symmetric or asymmetric. The first impedance may match the second impedance. The first and second impedances may, respectively, match the impedances of the first and second transmission lines. The first and/or second impedances may include a bidirectional switch, such as a transmission gate, to enable and disable the termination circuit. | 03-18-2010 |
20100066410 | LOW-LOSS IMPEDANCE-MATCHED SOURCE-FOLLOWER FOR REPEATING OR SWITCHING SIGNALS ON A HIGH SPEED LINK - Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-emphasis, by avoiding impedance discontinuities over process, voltage and temperature variations and by driving a broader range of loads, e.g., heavily capacitive loads. A circuit for switching or repeating signals on a single-ended or differential high speed link may comprise a source follower with input and output impedances matched to input and output transmission lines on the high speed link. The source follower is biased by a constant transconductance circuit, an external calibration circuit or other circuit to provide an essentially constant output impedance over process, voltage and temperature variations. | 03-18-2010 |
Patent application number | Description | Published |
20140061822 | SUBSTRATE BACKSIDE PEELING CONTROL - Structures and methods for reducing backside polysilicon peeling are disclosed. A structure includes a substrate having a first side and a second opposite side, a first dielectric layer on the second side of the substrate extending in a direction from an edge of the substrate towards a center of the substrate, a high-k layer on the first dielectric layer, and a polysilicon layer on the high-k layer. The first dielectric layer has a first innermost sidewall relative to the center of the substrate, and the high-k layer has a second innermost sidewall relative to the center of the substrate. The second innermost sidewall is within 2 millimeters from the first innermost sidewall in a direction parallel to the second side. The polysilicon layer extends towards the center of the substrate further than the first innermost sidewall. | 03-06-2014 |
20140162425 | METHOD OF FORMING DIELECTRIC FILMS USING A PLURALITY OF OXIDATION GASES - A method for forming a dielectric film is disclosed. The method includes (a) exposing a substrate to a first gas pulse having a first oxygen-containing gas in a chamber; (b) exposing the substrate to multiple consecutive second gas pulses having a second oxygen-containing gas in the chamber, wherein the first oxygen-containing gas is different from the second oxygen-containing gas; and (c) sequentially after (a) and (b), exposing the substrate to a third gas pulse having a metal-containing gas in the chamber. Steps (a), (b), and (c) may be repeated any number of times to form the dielectric film with a predetermined thickness. | 06-12-2014 |
20140191402 | Barrier Layer for Copper Interconnect - A device including a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 07-10-2014 |
20150044867 | Barrier Layer for Copper Interconnect - A device and a method of forming the device is provided. The device includes a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 02-12-2015 |
20150262870 | Barrier Structure for Copper Interconnect - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer. | 09-17-2015 |
20150262938 | Barrier Structure for Copper Interconnect - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer. | 09-17-2015 |
Patent application number | Description | Published |
20120234683 | ELECTROCHEMICAL PLATING - A method for electrochemical plating includes providing a wafer for an electrochemical plating (ECP) process, determining a wafer electrical property affecting the ECP process, adjusting a plating current or voltage applied in the ECP process based on the determined wafer electrical property, and electroplating the wafer with the adjusted plating current or voltage. A controller for controlling a power supply, and a system for electrochemical plating are also disclosed. | 09-20-2012 |
20140117547 | BARRIER LAYER FOR COPPER INTERCONNECT - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming a metal-containing layer in the dielectric layer, forming a barrier layer overlying the metal-containing layer, and performing a thermal process to form a metal oxide layer underlying the conductive layer. The metal oxide layer is a barrier layer formed at the boundary between the dielectric layer and the metal-containing layer. | 05-01-2014 |
20140231931 | IN-SITU NITRIDATION OF GATE DIELECTRIC FOR SEMICONDUCTOR DEVICES - A semiconductor substructure with improved performance and a method of forming the same is described. The semiconductor substructure includes a dielectric film over a substrate, the dielectric film including at least one metal dielectric layer, at least one oxygen-donor layer, and at least one nitride-incorporation layer. | 08-21-2014 |
20140332962 | Device and Method for Reducing Contact Resistance of a Metal - A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side wall of the trench wherein the TaN layer has a greater concentration of nitrogen than tantalum, a Ta layer deposited on the TaN layer, and a Cu deposited on the Ta layer. The structure further includes a via integrated into the trench at bottom of the filled trench. In an embodiment, both the TaN layer and the Ta layer are formed with physical vapor deposition (PVD) wherein the TaN layer is formed with plasma sputtering a Ta target with an N | 11-13-2014 |
Patent application number | Description | Published |
20090232925 | CUTTING MOLD FOR RIGID-FLEXIBLE CIRCUIT BOARD AND METHOD FOR FORMING THE SAME - A cutting mold for removing two opposite superfluous rigid circuit boards from a rigid-flexible circuit board. A first cutter is connected to a first moldboard. A first barricade is connected to the first moldboard. The maximum vertical distance from the first barricade to the first moldboard exceeds that from the first cutter to the first moldboard. A second moldboard is opposite the first moldboard. The first and second moldboards move with respect to each other. A second cutter is connected to the second moldboard and corresponds to the first cutter. A second barricade is connected to the second moldboard and detachably abuts the first barricade. The maximum vertical distance from the second barricade to the second moldboard exceeds that from the second cutter to the second moldboard. The first and second cutters cut the superfluous rigid circuit boards when the first and second moldboards move toward each other. | 09-17-2009 |
20100254618 | Method for Accessing Image Data and Related Apparatus - A method for accessing image data is disclosed. The image data includes a plurality of pixel data arranged in rows and columns, and every specific amount of pixel data rows forms a pixel group. The method includes writing the image data into an N-line image data register row-by-row successively, and reading the pixel data of each pixel group in a block-row form for image compression. | 10-07-2010 |
20110038105 | LOCKING MECHANISM AND ELECTRONIC DEVICE - A locking mechanism and an electronic device are provided. The electronic device includes a first body, a second body, a moving module, and a locking mechanism. The moving module is disposed between the first body and the second body, so that the second body is rotatable and tiltable relative to the first body. The locking mechanism includes a first connecting member and a plug. When the plug is coupled with the first connecting member by a magnetic force, the second body is slidable relative to the first body. When the second body is tilted up to decouple the plug from the first connecting member, the plug interferes the moving module, so that the second body is not slidable relative to the first body. | 02-17-2011 |
20110063781 | MOVING MODULE AND ELECTRONIC DEVICE - A moving module and an electronic device are provided. The electronic device includes a first body, a second body, and the moving module disposed between the first and second bodies. The moving module includes a rail, a moving element, and an elastic element. The moving element is in contact with the rail. The elastic element is connected between the moving element and the first body. When the moving element moves from a first end of the rail to a curved portion of the rail, a force exerted on the elastic element by the moving element is gradually increased. When the moving element passes the curved portion, an elastic restoration force of the elastic element drives the moving element to move toward a second end of the rail. When the moving element reaches the first end or the second end, the first body and the second body interfere with each other. | 03-17-2011 |
Patent application number | Description | Published |
20140055143 | BATTERY TESTING SYSTEM WITH ENERGY CIRCULATION - A battery testing system with energy circulation includes a battery module to be tested, an electric power storage module, a bi-directional conversion module and a control module, and the control module controls the bi-directional conversion module to discharge the electric power storage module and charge the battery module to be tested, or discharge the battery module to be tested and charge the electric power storage module, so that the electricity can be fully and repeatedly used, and the electric power storage module can use a second-used power battery to save the cost of the electric power storage module while the battery testing system can be isolated from the grid of utility power to avoid creating a burden to the grid of the utility power. | 02-27-2014 |
20140153289 | Secondary Side Serial Resonant Full-Bridge DC/DC Converter - The present invention relates to a secondary side serial resonant full-bridge DC/DC converter, comprising: a transistor full-bridge unit, a transformer unit, a resonant unit, a rectifying unit, and an output unit. Particularly, in the present invention, a resonant inductor and a resonant capacitor of the resonant unit and a load resistor of the output unit constitute a serial resonant circuit having a serial resonant frequency; therefore, when the circuit frequency is operated on the serial resonant frequency, the resonant inductor impedance would be offset by the resonant capacitor impedance, such that the circuit is operated in the zero current switch (ZCS) region, and the output voltage variation can be controlled in ±0.2%. Moreover, through the serial resonant circuit, the issue about the resonant components hard to be designed due to their small characteristic impedance can simultaneously be improved. | 06-05-2014 |
20140160798 | Voltage Converting Circuit of Active-Clamping Zero Voltage Switch - The present invention relates to a voltage converting circuit of active-clamping zero voltage switch, consisting of a transformed unit, a primary-side input unit, a second-side output unit, and a first switch, wherein the primary-side input unit has a clamping capacitor and a second switch, which are used for avoid from the production of spike voltage on the first switch when the first switch is turned off, so as to increase the voltage conversion efficiency of the voltage converting circuit. | 06-12-2014 |
20140169041 | DC TO DC CONVERTING CIRCUIT - The invention provides a DC to DC converting circuit, comprising: a transforming unit with a primary winding and a secondary winding; a bridge rectifier unit coupled to an input voltage, having a first output terminal and a second output terminal coupled to both side of the primary winding respectively; a first switch coupled between the input voltage and the first output terminal; a second switch coupled between the first output terminal and a ground terminal; a third switch coupled between the input voltage and the second output terminal; and a fourth switch coupled between the second output terminal and the ground terminal; an output unit paralleled to the secondary winding; and a clamping unit coupled to the input voltage and paralleled to the bridge rectifier unit, having an auxiliary switch coupled to the input voltage; and a clamping capacitor coupled between the auxiliary switch and the ground terminal; wherein the auxiliary switch is turned on when operation statuses of the first switch and the fourth switch or the second switch and the third switch are changed. | 06-19-2014 |
Patent application number | Description | Published |
20100034536 | Apparatus And Method For Medium Access Control In An Optical Packet-Switched Network And The Network Thereof - Disclosed is an apparatus and method for medium access control (MAC) in an optical packet-switched network. The MAC apparatus may comprise a bandwidth allocation module and an MAC processor. The bandwidth allocation module determines a data transmission limit based on a probabilistic quota plus credit mechanism for each node of the network, dynamically informs all downstream nodes of unused quota and allows the downstream nodes use remaining bandwidths of the upstream node. Through a control message carried by a control channel, the MAC processor determines uploading, downloading and data erasing for a plurality of data channels, and updates the corresponding contents in the control message. | 02-11-2010 |
20100067376 | Distributed Controlled Passive Optical Network System And Bandwidth Control Method Thereof - Disclosed is a distributed controlled passive optical network system and bandwidth control method thereof. The system comprises an optical line terminal (OLT), plural optical network units (ONUs) and a splitter with combiner. Each ONU has a first Tx/Rx for respectively transmitting and receiving data packets on an upstream data channel and a downstream data channel, and a second Tx/Rx for transmitting and receiving control signals/commands on a control channel. Upstream data of each ONU is carried by the upstream data channel and sent to the OLT through the splitter with combiner. Downstream data of the OLT is carried by the downstream data channel and sent to corresponding ONUs through the splitter with combiner. With the control signals/commands carried by the control channel, the required information of network status among the ONUs is provided | 03-18-2010 |
20120228618 | Thin Film Transistor Structure - A thin film transistor (TFT) structure is provided. The TFT comprises a gate, a first electrode, a second electrode, a dielectric layer, and a channel layer. By overlapping the area between the first electrode and the gate, the TFT structure acquires a parasitic capacitor that is unaffected by manufacture deviations. Therefore, the TFT needs no compensation capacitor, thereby, increasing the aperture ratio of the TFT. | 09-13-2012 |
Patent application number | Description | Published |
20090027371 | PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME - A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer. | 01-29-2009 |
20110316830 | PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME - A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer. | 12-29-2011 |
20140051200 | METHOD FOR FABRICATING PHOTO DETECTOR - A photo detector and related fabricating method are disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer. The patterned conductive layer is disposed on the dielectric layer. The inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region. The first electrodes are electrically connected to the first patterned semiconductor layer. | 02-20-2014 |
Patent application number | Description | Published |
20120257351 | ADJUSTING DEVICE OF ADJUSTING A VIEW ANGLE OF A PANEL MODULE AND COMPUTER SYSTEM HAVING THE SAME - An adjusting device includes a rotating mechanism disposed between a base and a supporter for adjusting an angle between the supporter and the base, a slide mechanism disposed on the base, and a turntable mechanism slidably disposed on the slide mechanism for holding a panel module, so that the panel module can slide relative to the base along the slide mechanism and for coaxially rotating the panel module relative to the base. A contacting component of the turntable mechanism is for pushing a constraining component of the slide mechanism to pivot relative to an axle, so as to separate the constraining component from a protruding portion of the rotating mechanism for releasing constraint on the supporter relative to the base. | 10-11-2012 |
20130107541 | ILLUMINATION STRUCTURE AND ASSEMBLY METHOD OF LIGHT BASE AND COVER | 05-02-2013 |
20130134466 | LED PACKAGE - An LED package is provided, which includes a base, a lighting device, and a sealing material. The lighting device is disposed on the base. The sealing material is disposed on the lighting material, and the out surface of the sealing material includes a plurality of micro-structures. The micro-structures comprise of protruded micro-structures, depressed micro-structures or any combination thereof. At least of a partial of a light from the lighting element is transmitted to an ambient through the micro-structure. | 05-30-2013 |
20130279198 | LIGHT MODULE AND LIGHT GUIDE DEVICE THEREOF - A light guide device includes N+1 light guide plates and N linear plane splitters. The light guide plates include a light outlet face, a light guiding face and a reflection face. The volume of the light guide device is defined by the light outlet face opposite to the light guiding face. The light guiding face has a plurality of first microstructures for diverting the light. The reflection face extends from the light outlet face toward a splitting portion. The linear plane splitters have a first and a second splitting portion. The first and second splitting portions of the i | 10-24-2013 |
20140021877 | LIGHT EMITTING CHIP AND LIGHT EMITTING DEVICE HAVING THE SAME - A light emitting chip operating under a DC power supply is provided. The light emitting chip includes a substrate and a plurality of light emitting elements. The light emitting elements are arranged on the substrate, and have the same or different area sizes. The light emitting elements are driven by a single driving voltage or sectionally driven by a plurality of driving voltages. | 01-23-2014 |
Patent application number | Description | Published |
20120326238 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure. | 12-27-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20130020657 | METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor. | 01-24-2013 |
20140035070 | METAL OXIDE SEMICONDUCTOR TRANSISTOR - A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure. | 02-06-2014 |
Patent application number | Description | Published |
20120147050 | METHOD OF ENTERING A COMMAND FOR ZOOMING IMAGE SHOWN ON TOUCH SCREEN AND TOUCH SCREEN DEVICE READING SUCH COMMAND - A method for zooming image shown in a touch screen includes reading information of a continuous writing locus formed on the touch screen; selecting a first group of points and a second group of points in the writing locus formed in time sequence; dealing with the first group and second group of points and obtaining a first radius and a second radius; comparing the first radius and the second radius to define a zooming command; executing the zooming command. A touch screen reading such writing locus into zooming command is also provided. | 06-14-2012 |
20120308736 | METHOD FOR PRODUCING OPTICAL WAVEGUIDE - A method for producing an optical waveguide includes following steps: firstly, providing a substrate and coating resins on the substrate to form a clad; secondly, providing a container filled with waveguide material and inject the waveguide material through a nozzle of the container to form a shape needed on the clad; thirdly, shining UV lights on the waveguide material to harden the waveguide material to form the waveguide. This new method uses less waveguide material and simplifies the steps. | 12-06-2012 |
20120315005 | OPTICAL WAVEGUIDE RIBBON WITH STACK-POSITIONING STRUCTURE - An optical waveguide ribbon includes a base layer integrated with a plurality of parallel optical cores. The optical waveguide ribbon includes a first surface and a second surface opposite to the first surface. The optical cores extend along a length direction and arrange along a width direction. A first positioning portion is exposed on the first surface with a given shape and a second positioning portion is exposed on the second surface and has a positioning dimension in width according to the given shape of the first positioning portion. | 12-13-2012 |
20130021217 | FLUIDIC DIPOLE ANTENNA - An antenna comprises: a closed and insulating receiving housing; a radiating portion received in the receiving housing and including a liquid metal; a grounding portion received in the receiving housing and including a liquid metal; a pair of wires respectively connected to the radiating portion and the grounding portion and extending out of the receiving housing; and two air chambers respectively located on the ends of the radiating portion and the grounding portion. | 01-24-2013 |
20140273567 | POWER JACK WITH A MOVABLE SOCKET COVER - A power jack, comprising an insulating housing, a socket which set in the bottom of the insulating housing, a movable socket cover which covers the socket and an elastic device between the socket cover and the socket which for ejecting the cover; the housing has a pair of limiting portions each having a button assembled thereto; the socket cover has an elastic arm which could clamp the limiting portion, so as to lock the socket cover; the elastic arm can be pushed away from the limiting portion by the button, so that the cover can be removed away from the socket. Therefore, it is convenient and safe for users to extract the plug with single hand. | 09-18-2014 |
Patent application number | Description | Published |
20090082667 | Bone examination apparatus and method - The invention discloses a bone examination apparatus which includes a shaking module, a multi-mode ultrasonic detecting module, and a processing module. The shaking module is disposed close to a distal end of an examinee's femur, for inputting a shaking signal to the distal end. The multi-mode ultrasonic detecting module is disposed close to a near end of the examinee's femur, for detecting the shaking signal through the examinee's femur at the near end and generating a detecting signal. Additionally, the processing module is connected to the shaking module and the multi-mode ultrasonic detecting module respectively, for determining the examinee's bone density in accordance with the shaking signal, the detecting signal, and a first criterion. | 03-26-2009 |
20090130679 | Automated system and method for processing genetic material - The invention discloses an automated system and method for processing genetic material. Additionally, the automated system and method of the invention can extract a target genetic material from a sample; amplifying a target nucleic acid sequence from the genetic material; detecting the target nucleic acid by an optical detection module to qualify and/or quantify the target nucleic acid immediately. | 05-21-2009 |
20100101237 | Temperature variation apparatus - The invention discloses a temperature variation apparatus for varying the temperature of a liquid. The temperature variation apparatus includes a metal tube, a power supply, a heat conductor, and a thermo-electric cooler (TEC). The liquid is poured into the metal tube. The power supply has an anode and a cathode respectively connected to two ends of the metal tube, so that the metal tube can be electrified to generate heat. The heat conductor encircles and contacts with the metal tube, and the thermo-electric cooler contacts with the heat conductor. | 04-29-2010 |
Patent application number | Description | Published |
20130095027 | CRYSTALLINE SILICON INGOT AND METHOD OF FABRICATING THE SAME - A crystalline silicon ingot and a method of fabricating the same are disclosed. The crystalline silicon ingot of the invention includes multiple silicon crystal grains growing in a vertical direction of the crystalline silicon ingot. The crystalline silicon ingot has a bottom with a silicon crystal grain having a first average crystal grain size of less than about 12 mm. The crystalline silicon ingot has an upper portion, which is about 250 mm away from said bottom, with a silicon crystal grain having a second average crystal grain size of greater than about 14 mm. | 04-18-2013 |
20130133569 | Crystal Growth Device - A crystal growth device includes a crucible and a heater setting. The crucible has a bottom and a top opening. The heater setting surrounds the crucible and is movable relative to the crucible along a top-bottom direction of the crucible and between first and second positions. The heater setting includes a first temperature heating zone and a second temperature heating zone higher in temperature than the first temperature heating zone. The heater setting is in the first position when the crucible is in the second temperature heating zone and in the second position when the crucible is in the first temperature heating zone. | 05-30-2013 |
20130136918 | CRYSTALLINE SILICON INGOT INCLUDING NUCLEATION PROMOTION LAYER AND METHOD OF FABRICATING THE SAME - A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm. | 05-30-2013 |
20140127496 | CRYSTALLINE SILICON INGOT INCLUDING NUCLEATION PROMOTION LAYER AND METHOD OF FABRICATING THE SAME - A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm. | 05-08-2014 |
20140186631 | SEED USED FOR CRYSTALLINE SILICON INGOT CASTING - The invention discloses a seed used for crystalline silicon ingot casting. A seed according to a preferred embodiment of the invention includes a crystal and an impurity diffusion-resistant layer. The crystal is constituted by at least one grain. The impurity diffusion-resistant layer is formed to overlay an outer surface of the crystal. A crystalline silicon ingot fabricated by use of the seed of the invention has significantly reduced red zone and yellow zone. | 07-03-2014 |
20150197873 | CRUCIBLE ASSEMBLY AND METHOD OF MANUFACTURING CRYSTALLINE SILICON INGOT BY USE OF SUCH CRUCIBLE ASSEMBLY - The invention provides a crucible assembly and method of manufacturing a crystalline silicon ingot by use of such crucible assembly. The crucible assembly of the invention includes a crucible body and a fiber textile article. The fiber textile article is made of a plurality of carbon fibers, and is loaded on a bottom of the crucible body. The fiber textile article has a plurality of intrinsic pores randomly arranged. | 07-16-2015 |
20150307361 | MULTICRYSTALLINE SILICON BRICK AND SILICON WAFER THEREFROM - Present disclosure provides a multicrystalline silicon (mc-Si) brick, including a bottom portion starting from a bottom to a height of 100 mm, a middle portion starting from the height of 100 mm to a height of 200 mm; and a top portion starting from the height of 200 mm to a top. A percentage of incoherent grain boundary in the bottom portion is greater than a percentage of incoherent grain boundary in the top portion. Present disclosure also provides a multicrystalline silicon (mc-Si) wafer. The mc-Si wafer includes a percentage of non-Σ grain boundary from about 60 to about 75 and a percentage of Σ3 grain boundary from about 12 to about 25. | 10-29-2015 |
20150361577 | METHOD OF CASTING INGOT AND CONTAINING DEVICE OF INGOT CASTING FURNACE FOR CONTAINING MATERIALS OF INGOT - A method of casting an ingot includes the following steps: place solid silicon raw materials on a bottom of a containing device, wherein the containing device includes a container and a graphite layer provided on a surrounding wall and an inner bottom of the container, and the solid silicon raw materials are stacked upon the graphite layer on the inner bottom; heat the container to melt the solid silicon raw material into liquid state; cool the container from the bottom up till all of the silicon raw materials are crystallized and solidified. The solidified silicon raw materials become an ingot. Whereby, the graphite layer can effectively prevent impurities of the container from contaminating the ingot. | 12-17-2015 |