Patent application number | Description | Published |
20110185264 | LDPC DECODING WITH ON THE FLY ERROR RECOVERY - It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder. | 07-28-2011 |
20110191653 | QUASI-CYCLIC LDPC ENCODING AND DECODING FOR NON-INTEGER MULTIPLES OF CIRCULANT SIZE - In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the padded data over the decision and reliability information corresponding to the padded data during message passing. Zero padding is removed from the decoded data. | 08-04-2011 |
20110252294 | IMPLEMENTATION OF LDPC SELECTIVE DECODING SCHEDULING - A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group. | 10-13-2011 |
20120166912 | INTERLEAVING PARITY BITS INTO USER BITS TO GUARANTEE RUN-LENGTH CONSTRAINT - RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved. | 06-28-2012 |
20120246536 | LDPC SELECTIVE DECODING SCHEDULING USING A COST FUNCTION - A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes. | 09-27-2012 |
20120304036 | MANUFACTURING TESTING FOR LDPC CODES - An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding. | 11-29-2012 |
20130246880 | LDPC SELECTIVE DECODING SCHEDULING USING A COST FUNCTION - A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes. | 09-19-2013 |
20140122965 | MULTIPLE INTERLEAVERS IN A CODING SYSTEM - Second interleaved data is de-interleaved using a second interleaving mapping to obtain encoded data. The second interleaved data includes a copy of constrained data in the same sequence and having the same values as the constrained data. Also, the portion of the second interleaved data that includes the copy of the constrained data satisfies a modulation constraint associated with limiting a number of consecutive events to a maximum number of consecutive events. The encoded data is decoded to obtain first interleaved data and the first interleaved data is de-interleaved using a first interleaving mapping to obtain the constrained data, a copy of which is included in the second interleaved data, where the constrained data satisfies the modulation constraint. | 05-01-2014 |
20140140384 | MATCHING SIGNAL DYNAMIC RANGE FOR TURBO EQUALIZATION SYSTEM - A method for reducing a number of bits for representing a value is disclosed. A first value represented with a first number of bits is transformed to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits. The transformed second value is scaled by a scale factor to a third value. Transforming includes selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits. Transforming further includes saturating the first value to a most significant bit (MSB) within the selected target window and extracting bits within the selected target window from the saturated value. | 05-22-2014 |
20140143616 | DEFECT SCAN AND MANUFACTURE TEST - A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold. | 05-22-2014 |
20140181570 | SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS - An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate. | 06-26-2014 |
20140195877 | LDPC DECODING WITH ON THE FLY ERROR RECOVERY - It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed on the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed on the data associated with the decoder. | 07-10-2014 |
20140200849 | DIVERSITY LOOP DETECTOR WITH COMPONENT DETECTOR SWITCHING - Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset. | 07-17-2014 |
20140237329 | Ratio-Adjustable Sync Mark Detection System - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system. | 08-21-2014 |
20140268400 | Systems and Methods for Loop Feedback - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing loop feedback in a data processing system. | 09-18-2014 |
20140281790 | Systems and Methods for Multi-Stage Encoding Of Concatenated Low Density Parity Check Codes - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for multi-stage encoding for concatenated low density parity check codes. | 09-18-2014 |
20140286149 | Automatic On-Drive Sync-Mark Search and Threshold Adjustment - A hard disk drive includes a processor to automatically adjust a threshold level for finding sync-marks. The processor determines all possible sync-mark patterns for a particular pattern length and analyzes each pattern with reference to real world data. The pattern with the largest distance gap is used. The threshold level is then adjusted dynamically to produce the lowest possible failure rate for the given pattern. | 09-25-2014 |
20140327981 | MARGINING DECODING UTILIZING SOFT-INPUTS - Determining a parameter associated with whether a portion of a storage device is defective is disclosed. Determining comprises: obtaining known data associated with the portion; reading back from the portion to produce a read-back waveform; decoding the read-back waveform, including producing statistical information; and determining a parameter associated with whether the portion is defective based at least in part on the statistical information. | 11-06-2014 |
20140362463 | Timing Error Detector with Diversity Loop Detector Decision Feedback - Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset. | 12-11-2014 |
20150019926 | MANUFACTURING TESTING FOR LDPC CODES - An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding. | 01-15-2015 |
20150033095 | BUFFER MANAGEMENT IN A TURBO EQUALIZATION SYSTEM - A plurality of partially-decoded codewords that have been processed at least once by a first and a second error correction decoder is stored. A plurality of metrics associated with how close a corresponding partially-decoded codeword is to being successfully decoded is stored. From the plurality of partially-decoded codewords, a codeword having a metric indicating that that codeword is the closest to being successfully decoded by the first error correction decoder and the second error correction decoder is selected. The selected codeword is output to the first error correction decoder. | 01-29-2015 |
20150089323 | ERROR RECOVERY USING ERASURES FOR NAND FLASH - Error correction decoding is performed on a codeword where the codeword is unable to be successfully decoded. One or more bits in the codeword are selected to be replaced with an erasure. The selected bits in the codeword is/are replaced with an erasure to obtain a codeword with one or more erasures. Error correction decoding is performed on the codeword with one or more erasures. | 03-26-2015 |