Patent application number | Description | Published |
20110187240 | Piezoelectronic device and method of fabricating the same - A piezoelectronic device and a method of fabricating the same are disclosed. The piezoelectronic device of the present invention comprises: a plurality of carbon nanotubes; at least one piezoceramic layer covering the plurality of carbon nanotubes; and a supporting material for supporting the carbon nanotubes and disposed between the carbon nanotubes, the supporting layer being coated with at least one piezoceramic layer, wherein the plurality of carbon nanotubes is arranged in a comb-shape. The piezoelectronic device of the present invention is advantageous in having excellent elasticity (durability) and excellent piezoelectronical property. The induced current obtained from the piezoelectronic device of the present invention is about 1.5 μA or above as well as induced voltage being over 1V when the size of the piezoelectronic block is 2.5 mm×1 mm×1 mm (length×width×height). | 08-04-2011 |
20110194990 | Method of fabrication visible light absorbed TiO2/CNT photocatalysts and photocatalytic filters - A method of fabricating visible light absorbed TiO | 08-11-2011 |
20110214264 | PIEZOELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - A piezoelectronic device and a method of fabricating the same are disclosed. The piezoelectronic device of the present invention comprises: a plurality of carbon nanotubes; at least one piezoceramic layer covering the plurality of carbon nanotubes; and a supporting material for supporting the carbon nanotubes and disposed between the carbon nanotubes, the supporting layer being coated with at least one piezoceramic layer, wherein the plurality of carbon nanotubes is arranged in a comb-shape. The piezoelectronic device of the present invention is advantageous in having excellent elasticity (durability) and excellent piezoelectronical property. The induced current obtained from the piezoelectronic device of the present invention is about 1.5 μA or above as well as induced voltage being over 1V when the size of the piezoelectronic block is 2.5 mm×1 mm×1 mm (length×width×height). | 09-08-2011 |
20120013223 | MICRO ELECTRIC GENERATOR, METHOD OF PROVIDING THE SAME, AND ELECTRIC GENERATING DEVICE - A micro electric generator is disclosed, which comprises: at least one electrically conductive fiber, and at least one piezoelectric ceramic layer covering on the surface of that at least one electrically conductive fiber. When a mechanical force is applied to deform the electrically conductive fiber covered with the piezoelectric ceramic layer, electric energy is generated. Also, a method of fabricating the said micro electric generator and an electric generating device are disclosed. | 01-19-2012 |
20120091539 | FACET-FREE SEMICONDUCTOR DEVICE - An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free. | 04-19-2012 |
20120248510 | BACKSIDE BEVEL PROTECTION - The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate. | 10-04-2012 |
20120289040 | FABRICATION METHODS OF INTEGRATED SEMICONDUCTOR STRUCTURE - An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit. | 11-15-2012 |
20130095647 | BACKSIDE BEVEL PROTECTION - A method of fabricating an integrated circuit device is provided. The method includes forming a replacement gate structure with a dummy polysilicon layer on a first surface of a substrate. The method further includes depositing a dielectric layer by a thermal process to form offset spacers on two opposing sides of the replacement gate structure, wherein the dielectric layer is deposited on the first surface and a second surface opposing the first surface of the substrate. The method further includes removing the dummy polysilicon layer from the replacement gate structure, wherein the dielectric layer on the second surface of the substrate protects the second surface of the substrate during the removing step. | 04-18-2013 |
20130234255 | Spacer Elements for Semiconductor Device - The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element. | 09-12-2013 |
20140246728 | SPACER ELEMENTS FOR SEMICONDUCTOR DEVICE - The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element. | 09-04-2014 |
20140248752 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING SPACER ELEMENTS - The present disclosure describes a method of fabricating semiconductor device including providing a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is formed on the substrate abutting the first gate stack. In an embodiment, a source/drain region is then formed. A second spacer element is then formed is adjacent the first spacer element. The second spacer element has a second height from the surface of the substrate, and the first height is greater than the second height. In embodiments, the second spacer element is used as an etch stop in forming a contact to the source/drain region. | 09-04-2014 |
20140291768 | SPACER ELEMENTS FOR SEMICONDUCTOR DEVICE - The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element. | 10-02-2014 |