Patent application number | Description | Published |
20130052809 | PRE-CLEAN METHOD FOR EPITAXIAL DEPOSITION AND APPLICATIONS THEREOF - A method for fabricating an epitaxizl structure is provided, wherein the method comprises steps as follows: a reactive gas containing nitrogen and fluorine atoms is firstly applied to react with an oxygen-atom-containing residue residing on a surface of a substrate so as to form a solid compound on the surface. Subsequently, an anneal process is performed to sublimate the solid compound. A semiconductor deposition process is then performed on the substrate. | 02-28-2013 |
20130115777 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURES - A manufacturing method for semiconductor structures includes providing a substrate having a first region and a second region defined thereon, forming a plurality of first patterns in the first region and at least a second pattern in the second region, forming a plurality of first spacers respectively on sidewalls of the first patterns and at least a second spacer on a sidewall of the second pattern, forming a patterned protecting layer in the second region, removing the first patterns from the first region to form a plurality of first masking patterns in the first region and at least a second masking pattern in the second region, and transferring the first masking patterns and the second masking pattern to the substrate. | 05-09-2013 |
20130200470 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures. | 08-08-2013 |
20130200483 | FIN STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a fin structure is provided. The method includes forming a hard mask material layer on a substrate, and then patterning the hard mask material layer to form a first hard mask layer. Thereafter, a portion of the substrate is removed to form two trenches, wherein a remaining substrate forms a fin between the trenches. Afterwards, an insulating layer is formed in each trench, wherein the insulating layers expose an upper portion of the fin. Further, the upper portion of the fin is trimmed, so that the trimmed upper portion is narrower than a lower portion of the fin, and a fin structure having an inverse T shape is formed. | 08-08-2013 |
20130240956 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device. | 09-19-2013 |
20130285146 | SEMICONDUCTOR DEVICES - Semiconductor devices include a substrate, a first gate structure and a second gate structure positioned on the substrate, and a first source/drain formed in the substrate respectively at two sides of the first gate structure and a second source/drain formed in the substrate respectively at two sides of the second gate structure. The first gate structure and the second gate structure include a same conductivity type. The first source/drain and the second source/drain are different. | 10-31-2013 |
20130299951 | FIN STRUCTURE - Provided is a fin structure including a fin and two insulating layers. The fin is disposed on a substrate, wherein an upper portion is narrower than a lower portion of the fin, and the fin has an inverse T shape. The insulating layers are disposed at two sides of the fin and at least expose the upper portion of the fin. | 11-14-2013 |
20140049699 | POLARIZING PLATE, TOUCH LIQUID CRYSTAL PANEL AND TOUCH DISPLAY - A polarizing plate includes a first substrate layer, a polarizing layer, a second substrate layer, a pressure sensitive adhesive layer and a light-shielding pattern. The polarizing layer is disposed on the first substrate layer. The second substrate layer is disposed on the polarizing layer, whereby the polarizing layer is located between the first substrate layer and the second substrate layer. The pressure sensitive adhesive layer is formed on a bottom surface of the first substrate layer, whereby the first substrate layer located between the polarizing layer and the pressure sensitive adhesives layer. The light-shielding pattern is formed between the second substrate layer and the pressure sensitive adhesives layer. | 02-20-2014 |
20140077229 | SEMICONDUCTOR STRUCTURE - A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures. | 03-20-2014 |
20140098035 | TOUCH DISPLAY MODULE AND ASSEMBLY METHOD THEREOF - A touch display module and an assembly method thereof are provided. The touch display module includes a backlight module, a cover plate, a display panel, a touch panel, a first adhesive layer, a second adhesive layer, a third adhesive layer and a fourth adhesive layer. The cover plate and the backlight module are disposed oppositely. The display panel is disposed between the backlight module and the cover plate. The touch panel is disposed between the display panel and the cover plate. The first adhesive layer covers around the backlight module, the display panel and the touch panel and a back portion of the backlight module. The second adhesive layer is disposed between the backlight module and the display panel. The third adhesive layer is disposed between the display panel and the touch panel. The fourth adhesive layer is disposed between the touch panel and the cover plate. | 04-10-2014 |
20140134543 | LAYOUT DECOMPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE APPLYING THE SAME - A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system. | 05-15-2014 |
20140201691 | LAYOUT DECOMPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE APPLYING THE SAME - A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system. | 07-17-2014 |
20140213066 | LAYOUT DECOMPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE APPLYING THE SAME - A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas. | 07-31-2014 |
20150044831 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first gate and a second gate are formed on a substrate. A first stress layer is formed to cover the first gate and the second gate. The first stress layer covering the first gate is etched to form a first spacer beside the first gate, but reserves the first stress layer covering the second gate. A first epitaxial layer is formed beside the first spacer. The first stress layer and the first spacer are entirely removed. A second stress layer is formed to cover the first gate and the second gate. The second stress layer covering the second gate is etched to form a second spacer beside the second gate, but reserves the second stress layer covering the first gate. A second epitaxial layer is formed beside the second spacer. The second stress layer and the second spacer are entirely removed. | 02-12-2015 |
20150044875 | METHOD OF FORMING PATTERN - A method of forming a pattern is disclosed. First, N kinds of different photomask patterns are provided. Thereafter, the N kinds of different photomask patterns are transferred to a hard mask layer by using at least N−1 kinds of light sources with different wavelengths, so as to form a hard mask pattern, wherein one of the at least N−1 kinds of light sources with different wavelengths is a light source with a wavelength of 193 nm, and N is an integer of three or more. | 02-12-2015 |
20150044879 | REMOVING METHOD - A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect. | 02-12-2015 |
20150072531 | METHOD FOR FORMING LAYOUT PATTERN - A method for forming a layout pattern includes the following processes. First, a first layout pattern consisting of mandrel patterns and dummy mandrel patterns, a second layout pattern consisting of geometric patterns, and a third layout pattern consisting of pad patterns and dummy pad patterns, are respectively defined on a first mask, a second mask, and a third mask. Then, the first layout pattern is transferred to form a first patterned layer. Afterwards, spacers having a first critical dimension are formed on the sidewalls of the first patterned layer so as to constitute loop-shaped patterns. Then, the third layout pattern is transferred to form a second patterned layer having a second critical dimension, wherein the second critical dimension is greater than the first critical dimension. Finally, the loop-shaped patterns, the pad patterns, and the dummy pad patterns are transferred into a target layer on the substrate. | 03-12-2015 |