Patent application number | Description | Published |
20150082121 | METHOD OF ERASE STATE HANDLING IN FLASH CHANNEL TRACKING - An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters. | 03-19-2015 |
20150113205 | Systems and Methods for Latency Based Data Recycling in a Solid State Memory System - Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. | 04-23-2015 |
20150113318 | Systems and Methods for Soft Data Utilization in a Solid State Memory System - Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. | 04-23-2015 |
20150117097 | Systems and Methods for Sub-Zero Threshold Characterization in a Memory Cell - Systems and method relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. | 04-30-2015 |
20150149698 | ELIMINATING OR REDUCING PROGRAMMING ERRORS WHEN PROGRAMMING FLASH MEMORY CELLS - Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur. | 05-28-2015 |
20150178149 | METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS - An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types. | 06-25-2015 |
20150178152 | PREVENTING PROGRAMMING ERRORS FROM OCCURRING WHEN PROGRAMMING FLASH MEMORY CELLS - Mis-programming of MSB data in flash memory is prevented by using ECC decoding logic on the flash die that error corrects the LSB values prior to the LSB values being used in conjunction with the MSB values to determine the proper reference voltage ranges. Error correcting the LSB page data prior to using it in combination with the MSB page data to determine the reference voltage ranges ensures that the reference voltage ranges will be properly determined and programmed into the flash cells. | 06-25-2015 |
20150199140 | INTERLEAVING CODEWORDS OVER MULTIPLE FLASH PLANES - An apparatus having an interface to a plurality of memories and a circuit is disclosed. Each memory generally has a plurality of planes and is nonvolatile. The circuit is configured to (i) generate a plurality of codewords by encoding a plurality of data units, (ii) generate a plurality of slices by parsing the codewords, (iii) generate a plurality of pages by interleaving the slices and (iv) write the pages in parallel into respective ones of the planes. | 07-16-2015 |