Young, TW
Albert Chia-Che Young, Taipei County TW
Patent application number | Description | Published |
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20110084817 | REMOTE CONTROL DEVICE AND RECOGNITION METHOD THEREOF - A remote control device and a recognition method thereof. The recognition method is adapted to the remote control device for generating a corresponding remote control signal to control an electronic device when the remote control device is moved. A sequence of sensing signal corresponding to movement of the remote control device is provided. The sequence of sensing signal is converted into a sequence of characteristic data. A sequential predetermined data matching the sequence of characteristic data is selected from a plurality of sequential predetermined data respectively corresponding to a respective remote control signal. The remote control signal corresponding to the matched sequential predetermined data is transmitted to the electronic device. | 04-14-2011 |
Bao-Ru Young, Zhubei City TW
Patent application number | Description | Published |
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20100109088 | BALANCE STEP-HEIGHT SELECTIVE BI-CHANNEL STRUCTURE ON HKMG DEVICES - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 05-06-2010 |
20110042750 | CONTROLLING GATE FORMATION FOR HIGH DENSITY CELL LAYOUT - Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion. | 02-24-2011 |
20110057267 | POLYSILICON DESIGN FOR REPLACEMENT GATE TECHNOLOGY - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature. | 03-10-2011 |
20110198675 | SPACER STRUCTURE OF A FIELD EFFECT TRANSISTOR - This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region. | 08-18-2011 |
20110237040 | MAIN SPACER TRIM-BACK METHOD FOR REPLACEMENT GATE PROCESS - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 09-29-2011 |
20110278646 | Balance Step-Height Selective Bi-Channel Structure on HKMG Devices - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 11-17-2011 |
20120001259 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess. | 01-05-2012 |
20120009754 | METHOD FOR MAIN SPACER TRIM-BACK - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 01-12-2012 |
20120025309 | OFFSET GATE SEMICONDUCTOR DEVICE - An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench. | 02-02-2012 |
20120025323 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width. | 02-02-2012 |
20120032238 | CONTACT ETCH STOP LAYERS OF A FIELD EFFECT TRANSISTOR - An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure. | 02-09-2012 |
20120074475 | METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region. | 03-29-2012 |
20120074498 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess. | 03-29-2012 |
20120280323 | DEVICE HAVING A GATE STACK - A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed. | 11-08-2012 |
20120292739 | INTEGRATED CIRCUIT HAVING SILICON RESISTOR AND METHOD OF FORMING THE SAME - An embodiment of the disclosure includes a method of forming an integrated circuit. A substrate having an active region and a passive region is provided. A plurality of trenches is formed in the passive region. A root mean square of a length and a width of each trench is less than 5 μm. An isolation material is deposited over the substrate to fill the plurality of trenches. The isolation material is planarized to form a plurality of isolation structures. A plurality of silicon gate stacks and at least one silicon resistor stack are formed on the substrate in the active region and on the plurality of isolation structures respectively. | 11-22-2012 |
20120299115 | SEMICONDUCTOR STRUCTURE WITH SUPPRESSED STI DISHING EFFECT AT RESISTOR REGION - A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate. | 11-29-2012 |
20130020651 | METAL GATE STRUCTURE OF A CMOS SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition. | 01-24-2013 |
20130029482 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width. | 01-31-2013 |
20130032884 | INTEGRATED CIRCUIT DEVICE HAVING DEFINED GATE SPACING AND METHOD OF DESIGNING AND FABRICATING THEREOF - A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm | 02-07-2013 |
20130056837 | SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE - A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure. | 03-07-2013 |
20130069174 | CONTACT FOR HIGH-K METAL GATE DEVICE - A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material. | 03-21-2013 |
20130099323 | METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region. | 04-25-2013 |
20130126977 | N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates. | 05-23-2013 |
20130154022 | CMOS Devices with Metal Gates and Methods for Forming the Same - A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device. | 06-20-2013 |
20130228834 | CONTACT ETCH STOP LAYERS OF A FIELD EFFECT TRANSISTOR - A field effect transistor, the field effect transistor includes a substrate including a surface and a gate structure including sidewalls and a top surface, the gate structure being positioned over the substrate. The field effect transistor further includes a spacer adjacent to the sidewalls of the gate structure and a first contact etch stop layer over the spacer and extending along the surface of the substrate. The field effect transistor further includes an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure. The field effect transistor further includes a second contact etch stop layer over at least a portion of the top surface of the gate structure. | 09-05-2013 |
20130234254 | METHOD OF HYBRID HIGH-K/METAL-GATE STACK FABRICATION - A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate. | 09-12-2013 |
20130244416 | SPACER STRUCTURE OF A FIELD EFFECT TRANSISTOR WITH AN OXYGEN-CONTAINING LAYER BETWEEN TWO OXYGEN-SEALING LAYERS - A method of fabricating a spacer structure which includes forming a dummy gate structure comprising a top surface and sidewall surfaces over a substrate and forming a spacer structure over the sidewall surfaces. Forming the spacer structure includes depositing a first oxygen-sealing layer on the dummy gate structure and removing a portion of the first oxygen-sealing layer on the top surface of the dummy gate structure, whereby the first oxygen-sealing layer remains on the sidewall surfaces. Forming the spacer structure further includes depositing an oxygen-containing layer on the first oxygen-sealing layer and the top surface of the dummy gate structure. Forming the spacer structure further includes depositing a second oxygen-sealing layer on the oxygen-containing layer and removing a portion of the second oxygen-sealing layer over the top surface of the dummy gate structure. Forming the spacer structure further includes thinning the second oxygen-sealing layer. | 09-19-2013 |
20130256805 | METAL GATE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THEREOF - A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer. | 10-03-2013 |
20130260547 | METHOD OF FABRICATING A METAL GATE SEMICONDUCTOR DEVICE - A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer. | 10-03-2013 |
20130264652 | Cost-Effective Gate Replacement Process - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device. | 10-10-2013 |
20130285150 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 10-31-2013 |
20130285151 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 10-31-2013 |
20130299913 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 11-14-2013 |
20130323893 | Methods for Forming MOS Devices with Raised Source/Drain Regions - A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor. | 12-05-2013 |
20130328115 | Contact for High-K Metal Gate Device - An integrated circuit includes a semiconductor substrate including a source region and a drain region and a gate dielectric over the semiconductor substrate. A metal gate structure is over the semiconductor substrate and the gate dielectric and between the source and drain regions. The integrated circuit further includes an interlayer dielectric (ILD) over the semiconductor substrate. First and second contacts extend through the ILD and adjacent the source and drain regions, respectively, and a third contact extends through the ILD and adjacent a top surface of the metal gate structure. The third contact further extends into an undercut region of the metal gate structure. | 12-12-2013 |
20130328134 | Method and Apparatus for Improving Gate Contact - A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess. | 12-12-2013 |
20140017886 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width, and having a first gate width. The method includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width, and having a second gate width greater than the first gate width. The method further includes forming a first set of spacer structures on sidewalls of the first and second sets of gate electrodes. The method further includes forming a second set of spacer structures abutting the first set of spacer structures and removing a subset of the second set of spacer structures over the sidewalls of the second set of gate electrodes. | 01-16-2014 |
20140045310 | METHOD OF MAKING STRUCTURE HAVING A GATE STACK - A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region. | 02-13-2014 |
20140048886 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity. | 02-20-2014 |
20140103429 | Method and Structure to Boost MOSFET Performance and NBTI - The present disclosure provides one embodiment of a method forming a p-type field effect transistor (pFET) structure. The method includes forming a mask layer on a semiconductor substrate, the mask layer including an opening that exposes a semiconductor region of the semiconductor substrate within the opening; forming a n-type well (n-well) in the semiconductor region by performing an ion implantation of a n-type dopant to the semiconductor substrate through the opening of the mask layer; and performing a germanium (Ge) channel implantation to the semiconductor substrate through the opening of the mask layer, forming a Ge channel implantation region in the n-well. | 04-17-2014 |
20140183648 | Semiconductor Structures and Methods of Forming the Same - A structure and method of forming the structure is disclosed. According to an embodiment, a structure includes three devices in respective three regions of a substrate. The first device comprises a first gate stack, and the first gate stack comprises a first dielectric layer. The second device comprises a second gate stack, and the second gate stack comprises a second dielectric layer. The third device comprises a third gate stack, and the third gate stack comprises a third dielectric layer. A thickness of the third dielectric layer is less than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A gate length of the third gate stack differs in amount from a gate length of the first gate stack and a gate length of the second gate stack. | 07-03-2014 |
20140203373 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 07-24-2014 |
20140203374 | N/P Boundary Effect Reduction for Metal Gate Transistors - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates. | 07-24-2014 |
20140246732 | Circuit Incorporating Multiple Gate Stack Compositions - An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region. | 09-04-2014 |
20140252455 | Structure And Method For Static Random Access Memory Device Of Vertical Tunneling Field Effect Transistor - The present disclosure provides one embodiment of a SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters. The pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel. | 09-11-2014 |
20140252504 | Method for Fabricating a Semiconductor Device - A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well. | 09-11-2014 |
20140264725 | SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI) - The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots. | 09-18-2014 |
20140299937 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width. Each gate electrode of the first set of gate electrodes has a first gate width. The method further includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width. Each gate electrode of the second set of gate electrodes has a second gate width greater than the first gate width. | 10-09-2014 |
20140317581 | REVISING LAYOUT DESIGN THROUGH OPC TO REDUCE CORNER ROUNDING EFFECT - The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received. The first layout design includes a plurality of gate lines and an active region that overlaps with the gate lines. The active region includes at least one angular corner that is disposed adjacent to at least one of the gate lines. The first layout design for the semiconductor device is revised via an optical proximity correction (OPC) process, thereby generating a second layout design that includes a revised active region with a revised corner that protrudes outward. Thereafter, the semiconductor device is fabricated based on the second layout design. | 10-23-2014 |
20140332893 | Integrated Circuit Device Having Defined Gate Spacing And Method Of Designing And Fabricating Thereof - A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm | 11-13-2014 |
20140367802 | SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE - An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure. | 12-18-2014 |
20140374835 | METAL GATE SEMICONDUCTOR DEVICE - A semiconductor device including a first gate structure associated with a first type of transistor and a second gate structure of a second type of transistor. The first gate structure includes a capping layer, a first metal layer having a first type of work function on the capping layer, and a second metal layer having a second type of work function, overlying the first metal layer and a fill layer on the second metal layer. The second type of work function is different than the first type of work function. The second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric, and the fill layer on the second metal layer. | 12-25-2014 |
20150021672 | CONTACT FOR HIGH-K METAL GATE DEVICE - An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity. | 01-22-2015 |
20150118809 | METHOD OF MAKING STRUCTURE HAVING A GATE STACK - A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor. | 04-30-2015 |
20150132902 | POLYSILICON DESIGN FOR REPLACEMENT GATE TECHNOLOGY - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature. | 05-14-2015 |
20150155286 | Structure and Method For Statice Random Access Memory Device of Vertical Tunneling Field Effect Transistor - Forming an SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters, the pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel. | 06-04-2015 |
20150214115 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate. | 07-30-2015 |
20150255352 | Semiconductor Structures and Methods of Forming the Same - A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate. | 09-10-2015 |
20150270269 | METAL GATE STRUCTURE OF A CMOS SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate comprising an isolation region surrounding a P-active region and an N-active region. The semiconductor device also includes an N-metal gate electrode comprising a first metal composition over the N-active region. The semiconductor device further includes a P-metal gate electrode. The P-metal gate electrode includes a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion includes the first metal composition. The bulk portion includes a second metal composition different from the first metal composition. | 09-24-2015 |
20150318367 | Controlling Gate Formation for High Density Cell Layout - Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions. | 11-05-2015 |
20150325669 | Cost-Effective Gate Replacement Process - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device. | 11-12-2015 |
20150333150 | METHOD OF FABRICATING A TRANSISTOR USING CONTACT ETCH STOP LAYERS - A method for fabricating a field-effect transistor includes forming a spacer adjacent to sidewalls of a gate structure. The method further includes forming silicide regions in a substrate adjacent to the spacer. The method further includes depositing a first interlayer dielectric layer over the substrate. The method further includes exposing a top surface of the gate structure. The method further includes depositing a contact etch stop layer over the first interlayer dielectric layer and the top surface of the gate structure. The method further includes patterning the contact etch stop layer to remove a portion of the contact etch stop layer over the silicide regions, wherein the contact etch stop layer over the gate structure is maintained. | 11-19-2015 |
20150364459 | N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS - The present disclosure provides a semiconductor device. A first active region is formed in a substrate. The first active region is elongated in a first direction in a top view. A first gate is formed over the substrate. The first gate is elongated in a second direction in the top view. A portion of the first gate is located over the first active region. A second gate is formed over the substrate. The second gate is elongated in the second direction in the top view. A portion of the second gate is located over the first active region. The second gate is shorter than the first gate in the second direction. | 12-17-2015 |
20150364575 | SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI) - Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric. | 12-17-2015 |
Bao-Ru Young, Hsinchu County TW
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20140197496 | Semiconductor Structure with Suppressed STI Dishing Effect at Resistor Region - An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate. The first width is less than the second width. The first STI feature has an etch-resistance less than that of the second STI feature. | 07-17-2014 |
20150262825 | METHODS OF FABRICATING MULTIPLE GATE STACK COMPOSITIONS - A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over the first region, the second region, and the third region. The first interfacial layer is etched to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region. Etching of the first interfacial layer defines a gate stack within the third region. After the etching of the first interfacial layer, a second interfacial layer is formed over at least a portion of the second region. The second interfacial layer is etched to define a gate stack within the second region. After the etching of the second interfacial layer, a third interfacial layer is formed on the substrate over at least a portion of the first region to define a gate stack within the first region. | 09-17-2015 |
Ben-Li Young, Hsinchu City TW
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20150105262 | MAGNETOELECTRIC EFFECT MATERIAL AND METHOD FOR MANUFACTURING SAME - The invention provides the Magnetoelectric Effect Material consisted of a single isotope, the alloy of isotopes, or the compound of isotopes. The invention applies enrichment and purification to increase the isotope abundance, to create the density of nuclear exciton by irradiation, and therefore increase the magnetoelectric effect of the crystal of single isotope, the alloy crystal of isotopes and the compound crystal of isotopes. The invention provides the manufacturing method including the selection rules of isotopes, the fabrication processes and the structure of composite materials. The invention belongs to the area of the nuclear science and the improvement of material character. The invention using the transition of entangled multiple photons to achieve the delocalized nuclear exciton. The mix of selected isotopes adjusts the decay lifetime of nuclear exciton and the irradiation efficiency to generate the nuclear exciton. | 04-16-2015 |
Boa-Ru Young, Zhubei TW
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20140291769 | Cost-Effective Gate Replacement Process - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device. | 10-02-2014 |
Chang-Due Young, Kaohsiung City TW
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20150138976 | PACKET PROCESSING APPARATUS USING PACKET PROCESSING UNITS LOCATEDAT PARALLEL PACKET FLOW PATHS AND WITH DIFFERENT PROGRAMMABILITY - A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, and a traffic manager. The ingress packet processing circuit processes ingress packets received from ingress ports. The egress packet processing circuit processes egress packets to be forwarded through egress ports. The traffic manager deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit and the egress packet processing circuit includes a first packet processing unit located at a first packet flow path, and a second packet processing unit located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit is higher than programmability of the second packet processing unit. | 05-21-2015 |
20150139235 | PACKET PROCESSING APPARATUS USING ACTION COMMAND PARAMETERIZATION - A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, a traffic manager, and a processor. The ingress packet processing circuit processes an ingress packet received from an ingress port to generate at least one parameter. The egress packet processing circuit has at least one programmable look-up table, refers to the at least one parameter to determine at least one action command set, and executes the at least one action command set for generating an egress packet to be forwarded through an egress port. The traffic manager is coupled between the ingress packet processing circuit and the egress packet processing circuit. The processor programs the at least one programmable look-up table. No action command in the at least one action command set is transmitted from the ingress packet processing circuit to the egress packet processing circuit through the traffic manager. | 05-21-2015 |
Chieh-Neng Young, Tainan City TW
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20120089372 | APPARATUS AND METHOD FOR ADAPTIVE TIME-FREQUENCY ANALYSIS - An apparatus and a method for adaptive adaptive time-frequency analysis are suitable for nonlinear and nonstationary signal analyses. The method includes the following steps. A plurality of positions of local extrema of a signal is determined. Average frequencies between the local extrema and mean energy distribution corresponding thereto are estimated according to the positions of the local extrema of the signal. The estimated instantaneous energy distribution of the signal is determined by way of optimization according to each of the mean energy distribution between the local extrema. Finally, an instantaneous frequency of the signal is estimated according to the estimated instantaneous energy distribution of the signal. | 04-12-2012 |
20120310600 | APPARATUS AND METHOD FOR PROCESSING SIGNAL - An apparatus and a method for processing signal are provided. The signal processing apparatus comprises an input interface and a processing unit. The input interface receives smoothing parameters and a to-be-separated signal. The processing unit establishes an upper extreme envelope and a lower extreme envelope of the to-be-separated signal, and calculates a mean envelope between the upper extreme envelope and the lower extreme envelope. The processing unit performs smoothing according to the smoothing parameters and the mean envelope to generate a smoothed mean envelope, and determines a trend component or a non-trend component according to the smoothed mean envelope. | 12-06-2012 |
20140018648 | BLOOD PARAMETER MEASURING DEVICE AND METHOD FOR MEASURING BLOOD PARAMETER - A blood parameter measuring device and a method for measuring a blood parameter are provided. The blood parameter measuring device includes an emitted source, a receiver module, and an actuator. The emitted source is disposed at a side of a tissue to be analyzed and provides at least two different wavelengths of radiation. The receiver module is disposed at another side of the tissue to be analyzed to receive the attenuated radiation produced by the emitted source. The actuator is connected to at least one of the emitted source and the receiver module. The actuator generates a driving force to make the emitted source and the receiver module contacts the tissue to be analyzed, thereby imposing a normal stress on a surface of the tissue to be analyzed to change a wave path between the emitted source and the receiver module. | 01-16-2014 |
Chin-Huai Young, Tao-Yuan TW
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20090068496 | LED STRUCTURE - The present invention discloses an improved LED structure and comprises: a circuit brace, a bowl member; a light chip; a welding line; a packing mask; and a photocatalystic agent. The volume of an LED is smaller so as to be convenient for installment. Compared the present invention to a light tube with same power, the present invention can be added several LEDs in order to increase the curve surface area to contact air, so that the functions of disinfection, deodorization, and mildewproof can be effectively achieved. | 03-12-2009 |
20100200891 | LED STRUCTURE - The present invention discloses an improved LED structure and comprises: a LED chip; a wire; a packing mask; and a photocatalytic agent. The volume of an LED is smaller so as to be convenient for installation. Compared to a conventional LED with same power, the present invention increases the total contact surface area that contacts air, so that the functions of disinfection, deodorization, and mildewproofing can be effectively achieved. | 08-12-2010 |
Chin-Huai Young, Taipei City TW
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20080276928 | WINDOW STRUCTURE - A window structure is provided, comprising a frame, a solar energy board, a plate and a heat isolation film. The solar energy board is disposed in the frame. The plate is disposed in the frame corresponding to the solar energy board, wherein an isolation chamber is formed between the plate and the solar energy board. The heat isolation film is disposed between the solar energy board and the plate, and divides the isolation chamber. | 11-13-2008 |
Chin-Huai Young, Taipel TW
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20110265854 | PHOTOVOLTAIC MODULE - A photovoltaic module is provided. The photovoltaic module includes a solar panel, a reflective insulating element, and a plate. The reflective insulation element reflects the sunlight, and the reflected sunlight passes through the solar panel, which results in an enhancement of photovoltaic effects occurred in the solar panel. A gap is disposed between the plate and the reflective insulation element, forming a hollow layer to obstruct heat conduction between the reflective insulation element and the plate effectively. The power generating efficiency and thermal-insulating ability of the photovoltaic module provided in the invention are improved. | 11-03-2011 |
Chiu-Chung Young, Dali City TW
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20100275826 | Method for Increasing Organic Carbon Content of Soil Employing Industrial Wastewater and Green Manure Crops - A method for increasing the organic carbon content of soil employing industrial wastewater and green manure crops comprises adding industrial wastewater containing cyclic phenolic substances or nitrogen compounds or a mixture of the above two kinds of industrial wastewater into the soil with the application of green manure crops to increase the organic carbon content of the soil and facilitate the humification thereby stabilizing the organic carbon in the soil. | 11-04-2010 |
Chorng-Lih Young, Taoyuan County TW
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20150236150 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided. | 08-20-2015 |
Christopher Young, Taipei City TW
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20130103226 | REHABILITATION DEVICE - A rehabilitation device includes a moving body, a motor, a control system and a sensor module. The moving body has a housing and a moving mechanism. The motor, disposed in the housing, connects to the moving mechanism and drives the moving mechanism. The control system is disposed in the housing and coupled to the motor. | 04-25-2013 |
Christopher Young, Taipei TW
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20110118898 | Rehabilitation Device - A rehabilitation device includes a moving body, a motor, a control system and a sensor module. The moving body has a housing and a moving mechanism. The motor, disposed in the housing, connects to the moving mechanism and drives the moving mechanism. The control system is disposed in the housing and coupled to the motor. The sensor module is disposed on the moving body and coupled to the control module. The control system controls the operation of the motor to move the moving body according to information detected by the sensor module. | 05-19-2011 |
Chune-Ching Young, Taoyuan County TW
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20150090373 | ALUMINUM ALLOYS WITH HIGH STRENGTH AND COSMETIC APPEAL - The disclosure provides an aluminum alloy including having varying ranges of alloying elements. In various aspects, the alloy has a wt % ratio of Zn to Mg ranging from 4:1 to 7:1. The disclosure further includes methods for producing an aluminum alloy and articles comprising the aluminum alloy. | 04-02-2015 |
Chune-Ching Young, Longtan Township TW
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20090136379 | MANUFACTURING METHOD FOR WIDE-RANGE FINE-GRAINED MAGNESIUM ALLOY THIN-SHEET MATERIAL - A manufacturing method for wide-range fine-grained magnesium alloy thin-sheet material is disclosed. The method includes an extrusion process and a rolling process. By the plastic deformation feature of the two processes, the wide-range fine-grained magnesium alloy thin-sheet material that satisfies the requirement of cases of 3C products with thickness of less than 1 mm is produced. Thus the method overcomes shortcomings of a conventional method that produces the material by a plurality passes of processes. Therefore, the manufacturing cost is reduced and the method is able to be applied to various industries. | 05-28-2009 |
Chung-Ping Young, Tainan City TW
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20140258731 | DATA ENCRYPTION SYSTEM AND METHOD - A data encryption method is implemented by a data encryption system including a processing unit and a plurality of operating units which are electrically connected to the processing unit. Each operating unit includes an encryption element and a memory element storing a plurality of encryption programs. Each encryption program has a different combination of encryption algorithm and encryption mode. The data encryption method includes steps of: selecting one of the encryption programs randomly by each encryption element; receiving, by each encryption element, one of a plurality of keys randomly generated; inputting an unencrypted data; dividing the unencrypted data into a plurality of unencrypted data blocks by the processing unit; and encrypting the unencrypted data blocks according to the selected encryption programs and received keys by the encryption elements, respectively, to generate an encrypted data. A data encryption system is also disclosed. | 09-11-2014 |
Fu-Hsing Young, Taipei TW
Guang-Huar Young, Taipei City TW
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20140162295 | Method and Biomarker for Detecting of Acute Kidney Injury - A method and a biomarker for detecting of acute kidney injury is provided, wherein the method of the present comprises the following steps: detecting a soluble form of hemojuvelin in a sample obtained from a subject, wherein when the soluble form of hemojuvelin is present in the sample, the subject is identified as having acute kidney injury. | 06-12-2014 |
Han-Ping Young, Hsinchu TW
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20090250348 | Droplet microfluidic transporting module - A droplet microfluidic transporting module adapted for transporting a droplet is disclosed to include one or a number of connectors and one or a number of microfluidic transporting platform. Each connector defines a passage extending in one or multiple predetermined directions, and a first driving electrode extending along one side of the passage for the contact of the droplet to be transported. The microfluidic transporting platform is detachably electrically connected with the connector, defining a channel in communication with the passage of the connector and having a second driving electrode extending along one side of the channel for the contact of the droplet to be transported. | 10-08-2009 |
Hong-Tsu Young, Taipei TW
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20120253694 | METHOD AND APPARATUS FOR JUDGING STATUS OF MECHANICAL SYSTEM - A method for judging the status of a mechanical system is provided. First, a vibration signal related to the mechanical system is provided. Subsequently, an empirical mode decomposition process is performed on the vibration signal, so as to generate a plurality of intrinsic mode functions. Plural target intrinsic mode functions are selected from the intrinsic mode functions. Based on the target intrinsic mode functions, the status of the mechanical system is judged. | 10-04-2012 |
Hsu-Wen Vincent Young, Taoyuan City TW
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20160120429 | METHOD AND SYSTEM FOR EXTRACTING VENTRICULAR FIBRILLATION SIGNALS IN ELECTROCARDIOGRAM - This invention discloses a system and a method for extracting VF signal in ECG recorded during uninterrupted CPR. The present invention provides a method for extracting a Ventricular fibrillation (VF) signal in Electrocardiography (ECG), comprising: receiving an ECG signal; adding a plurality of shadowing functions to the ECG signal, to obtain a plurality of modification signals; decomposing the plurality of modification signals by using an Empirical Mode Decomposition (EMD) method, to generate a plurality of Intrinsic Mode Functions (IMFs); calculating the sum of IMFs in different frequency regions based on time sequence, dividing by a number of the shadowing signal, to obtain a plurality of modification intrinsic mode functions; combining the plurality of modification IMFs with the same property, to obtain a shape function; modeling the shape functions to obtain a compression signal; and subtracting the compression signal from the ECG signal based on time sequence, to obtain the VF signal. | 05-05-2016 |
James Young, Taipei City TW
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20110241619 | DISTRIBUTED CHARGING SYSTEM AND METHOD FOR ELECTRICAL VEHICLE - The distributed charging system is for charging an energy storage device of an electrical vehicle operated within an operation region where a number of station or parking areas are arranged at intervals. The system contains a plurality of charging stations and fast charging devices where a charging station is provided at each station or parking area and at least a fast charging device is provided at each charging station. When the electrical vehicle is parked at a station or parking area, the electrical vehicle's energy storage device is quickly charged by the fast charging device there. Therefore, there is no additional and dedicated time spent for charging while the capacity, cost, weight, and size of the energy storage device could be reduced, making the electrical vehicle less costly, more compact, and with more extended operation time and distance. | 10-06-2011 |
20110248683 | ENERGY-EFFICIENT FAST CHARGING DEVICE AND METHOD - The energy-efficient fast charging method is applicable to an energy-efficient fast charging device having a power conversion module and at least a fast chargeable energy storage device. The power conversion module obtains and converts an input power from an external power source, and produces an internal DC power. The method contains the following steps. First, whether an external energy storage device is connected is detected. Then, if the presence of the external energy storage device is not detected, the internal fast chargeable energy storage device is charged by the internal DC power output from the power conversion module. Otherwise, the external energy storage device is charged by the internal DC power output from the power conversion module and the stored power of the fast chargeable energy storage device simultaneously. | 10-13-2011 |
20150152333 | APPARATUS FOR PYROLYZING WASTE PLASTIC INTO FUEL - An apparatus pyrolyzes waste plastics into fuel. The apparatus categorizes the waste plastic, and processes the categorized waste plastic to obtain kerosene, diesel fuel, gasoline etc. The apparatus includes a first heat exchange tank, a rough fuel storage tank, a second heat exchange tank, a diesel storage tank, and a kerosene storage tank. Combustible gas is extracted from the tanks via outlets thereof and stored in a gas storage tank. The combustible gas stored in the gas storage tank is fed into a combustion machine of a pyrolysis furnace of the apparatus. A fuel-water separate tank is connected to the bottom of the rough fuel storage tank to separate fuel from water. The separated fuel is recycled into the combustion machine to be burned again. Recycled paper with residual plastic films thereon has to be compressed into grains to facilitate a feeding operation. | 06-04-2015 |
James Patrick Young, Taoyuan Hsien TW
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20140024257 | HIGH DENSITY CONNECTOR STRUCTURE FOR TRANSMITTING HIGH FREQUENCY SIGNALS - A high density connector structure for transmitting high frequency signals having a first sub-assembly, a second sub-assembly, a shield plate, and a shield shell is disclosed. The first sub-assembly has a plurality of first contacts held in a first insulator, and the second sub-assembly has a plurality of second contacts held in a second insulator. The shield plate is positioned between the first and second contacts. At least one resilient arm extends from said shield plate and contacts at least one of the first contacts of the first sub-assembly. The shield shell at least partially surrounds the periphery of the first and second sub-assemblies. | 01-23-2014 |
20140080344 | CARD EDGE CONNECTOR - The invention relates to a card edge connector including an insulating body, a first fixing part, a second fixing part and a plurality of terminals. The terminals are respectively fixing on the first fixing part and the second fixing part in an insert molding manner. The first fixing part and the second fixing part are received and arranged in the insulating body. The first fixing part and the second fixing part respectively has at least one hook. At least one insertion slot is inwardly formed in the insulating body at a position corresponding to the hook; and the hooks are respectively pushed and fastened inwards towards the insertion slots, so that the first fixing part and the second fixing part are assembled and located on the insulating body. | 03-20-2014 |
Jenn-Shoou Young, Hsinchu TW
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20080281661 | Real-time Advertisement Displaying System and Method thereof - A method for displaying advertisements in a real-time manner includes the step of getting an external information having one of the image data and the audio data, the step of managing the external data, the step of generating triggered messages, the step of displaying the advertisements according to the triggered messages corresponding to the external data, and the step of recording a number of displayed times of the advertisements. With the abovementioned method, sights of observers may be significantly attracted by displayed advertisements. | 11-13-2008 |
20090109125 | IMAGE PROCESSING METHOD AND SYSTEM - An image processing method is disclosed. The method is applied to a display device including a plurality of series connection sub display devices. A video chip of each of the sub display devices sets a device ID for each of the corresponding sub display devices according to a setting signal. An image frame is retrieved from an image output device and is divided to a plurality of sub image frames according to the device IDs of each of the sub display devices. It is determined whether a switch signal has been detected. If the switch signal has not been detected, the sub image frames are respectively displayed in the sub display devices with a first video mode. If the switch signal has been detected, the sub image frames are respectively displayed in the sub display devices with a second video mode. | 04-30-2009 |
20090128524 | DISPLAY DEVICE CONTROL SYSTEMS AND METHODS - Display device control systems and methods are provided. The system includes at least a first display device and a control device wirelessly coupled to the first display device. The first display device has a first identification. The control device includes an input unit. The control device generates a second identification via the input unit, and wirelessly transmits the second identification to the first display device. The first display device determines whether the second identification conforms to the first identification, and if so, accepts the control from the control device. | 05-21-2009 |
Jenn-Shoou Young, Hsin-Chu City TW
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20090055766 | Content Scheduling Method and Scheduling Interface of Display - The invention discloses a content scheduling method and a scheduling interface of display, and a display with image retention removal. The content scheduling method creates a timer item with a program timer at least in a main menu of an on screen display (OSD), selects the program timer to pop up a program timer interface and inputs at least one content scheduling record. Moreover, the mentioned method includes the steps of popping up a repeat timer interface and then inputting a repeat content scheduling record or a multiple displays content scheduling record to the repeat timer interface if the scheduling record existing a repeat timer index. | 02-26-2009 |
Jiao-Saie Young, Taipei TW
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20100281205 | Micro Control Module For Universal Connection And Universal Connection Method Thereof - A micro control module for universal connection and a universal connection method thereof are provided. The micro control module includes a supporting interface module, a micro control unit, and a memory unit. The micro control unit is configured to read interface-setting data saved in the supporting interface module and save the interface-setting data into the memory unit. When a wireless transmission module is electrically connected to the micro control module, the micro control unit generates an identification result, selects the appropriate interface-setting data from the memory unit, and reads the corresponding initialization data from the supporting interface module, so as to initialize the wireless transmission module. | 11-04-2010 |
Kung-Chia Young, Tainan City TW
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20130171736 | BLOOD COAGULATION DETECTION DEVICE AND METHOD - A blood coagulation detection device includes a micro channel unit, an optical signal unit, an opto-electronic conversion circuit, an amplifier circuit, and a filter circuit. The micro channel unit has a sample detection area. The optical signal unit transmits a reference light to the micro channel unit so as to form a message light. The opto-electronic conversion circuit receives the message light and converts the message light into an electrical signal. The amplifier circuit is electrically connected to the opto-electronic conversion circuit for amplifying the electrical signal. The filter circuit is electrically connected to the amplifier circuit for filtering the amplified electrical signal. | 07-04-2013 |
Min-Li Wang Young, Taipei Hsien TW
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20090103231 | Stun gun with an extendable electric shock distance - A stun gun with an extendable electric shock distance has a high voltage electric arc generator and a conductive liquid supplier. The high voltage electric arc generator generates a high voltage electric arc. A conductive liquid fills with inside the conductive liquid supplier. When the conductive liquid is spurted from the conductive liquid supplier, the conductive liquid is passing through the high voltage electric arc. Since the conductive liquid has conductance, the conductive liquid spurted from the stun gun is able to extend an electric shock distance. | 04-23-2009 |
Moan Young, Hsinchu TW
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20090052139 | Heat-Dissipation Apparatus For Communication Device With Card Slot - A heat dissipation apparatus for communication device with card slot is provided. The heat dissipation apparatus is applicable to a communication platform to dissipate the heat generated by the card communication module to the housing case. The heat dissipation apparatus includes a heat-conductive bridge, and at least a soft heat-conductive plate. The soft heat-conductive plate covers the surface of the card communication module to conduct the heat generated by the chips of the card communication module to the heat-conductive bridge, and then to the metal housing case for dissipation. | 02-26-2009 |
Mu-Jen Young, Hsinchu County TW
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20140370689 | REACTION DEVICE AND MANUFACTURE METHOD FOR CHEMICAL VAPOR DEPOSITION - A reaction device for chemical vapor deposition is disclosed. The reaction device includes a chamber, a susceptor, an inlet pipe unit and an outlet pipe. The susceptor is disposed within the chamber. The inlet pipe unit includes a plurality of feeding openings horizontally facing the peripheral area of the susceptor to input at least one reaction gas into the chamber. The at least one reaction gas is guided to move from the peripheral area of the susceptor and along a surface of the susceptor to reach the center of the susceptor. The outlet pipe includes a discharge opening whose position is corresponding to the center of the susceptor so as to discharge the reaction gas flowing to the center of the susceptor out of the chamber. | 12-18-2014 |
Mu-Jen Young, Zhudong Township TW
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20130146801 | COMPOSITE MATERIAL WITH CONDUCTIVE AND FERROMAGNETIC PROPERTIES AND HYBRID SLURRY - In one embodiment of the disclosure, a composite material with conductive and ferromagnetic properties is provided. The composite material includes: 5 to 90 parts by weight of a conductive polymer matrix; and 0.1 to 40 parts by weight of iron oxide nanorods, wherein the iron oxide nanorods are ferromagnetic and have a length-to-diameter ratio of larger than 3. In another embodiment, a hybrid slurry is provided. The hybrid slurry includes a conductive polymer, and iron oxide nanorods, wherein the iron oxide nanorods are ferromagnetic and have a length-to-diameter ratio of larger than 3; and a solvent. | 06-13-2013 |
Neo Bob Chih Yung Young, Taipei TW
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20120033882 | Method of reducing the amount of black in an image - A method to reduce the amount of black in an image is disclosed. The method uses a computer to reduce or eliminate the amount of black in an original digital image. In the present invention, every three adjacent pixels are processed as a set, and the intensities of the RGB values are increased, respectively. | 02-09-2012 |
20140023219 | METHOD OF AND HEARING AID FOR ENHANCING THE ACCURACY OF SOUNDS HEARD BY A HEARING-IMPAIRED LISTENER - A method for enhancing the accuracy of sounds heard by a hearing-impaired listener is disclosed. The method for enhancing the accuracy of sounds heard by a hearing-impaired listener includes receiving an input sound, increasing or decreasing the energy of the high frequency section and then lowering the frequency of the high frequency section, and then combining the low high frequency section with the high frequency section of which the energy was increased/decreased and the frequency was lowered. | 01-23-2014 |
20140270289 | HEARING AID AND METHOD OF ENHANCING SPEECH OUTPUT IN REAL TIME - A method for enhancing speech output in real time is used in a hearing aid device. The input speech is divided into multiple audio segments first. Then each audio segment is analyzed for its attribute: high frequency, low frequency, or soundless. Low frequency segments are outputted without undergoing frequency processing. High frequency segments are outputted after undergoing frequency processing. All or some of the soundless segments are deleted without being outputted. The deletion of soundless segments can reduce the delay caused by the frequency processing of the high frequency segments. | 09-18-2014 |
20140286480 | METHOD OF PROCESSING TELEPHONE VOICE OUTPUT, SOFTWARE PRODUCT PROCESSING TELEPHONE SOUND, AND ELECTRONIC DEVICE WITH TELEPHONE FUNCTION - A method of processing telephone voice output is applied in an electronic device with telephone function. When any one of the two communicators is a hearing-impaired user, at least one of the electronic devices will obtain the corresponding voice adjustment parameters according to the receiver identification of the hearing-impaired user. Therefore, the voice adjusting program is able to process the voice in advance based on the voice adjustment parameters to help the hearing-impaired user hear better. | 09-25-2014 |
20140358530 | METHOD OF PROCESSING A VOICE SEGMENT AND HEARING AID - A method of processing a voice segment includes checking whether a voice segment is a vowel segment. If the voice segment is not a vowel segment, then the process checks whether the voice segment is a high frequency consonant or a low frequency consonant. If the voice segment is a high frequency consonant, then the voice segment will be processed to lower its frequency. | 12-04-2014 |
20150049879 | METHOD OF AUDIO PROCESSING AND AUDIO-PLAYING DEVICE - A method of audio processing lowers the frequency of a high frequency audio area of an input audio in order to generate a lowered frequency audio area. The lowered frequency audio area is combined with the input audio to generate an output audio such that the output audio comprises the high frequency audio area, a low frequency audio area, and a lowered frequency audio area. | 02-19-2015 |
20150076201 | WRISTBAND CONTAINER FOR AN EARPIECE - A wristband container for an earpiece is worn on a user's wrist. It is used for containing an earpiece. The wristband container for an earpiece includes a container main body, a first band, and a second band. The first band and the second band are connected to the container main body to form a circular space for the user's wrist. The first band and the second band are used to fix the wristband container for an earpiece on the user's wrist. The container main body has a containing space to contain an earpiece. | 03-19-2015 |
20150163600 | METHOD AND COMPUTER PROGRAM PRODUCT OF PROCESSING SOUND SEGMENT AND HEARING AID - A method of processing a sound segment is used in a hearing aid. If the sound segment is a high-frequency type, the high-frequency portion of the sound segment will be processed with a frequency lowering process. If the sound segment is a mixed-frequency type (between high-frequency and low-frequency), the energy of at least some portion of the high-frequency portion of the sound segment will be decreased and then processed with a frequency lowering process. | 06-11-2015 |
20150201057 | METHOD OF PROCESSING TELEPHONE VOICE OUTPUT AND EARPHONE - A method of processing telephone voice output is used in an earphone. This method includes obtaining a corresponding adjustment parameter according to the phone identification information of the hearing-impaired so as to make the processing module in the earphone process the voice according to the adjustment parameter in advance and enable the hearing-impaired to hear more clearly. | 07-16-2015 |
20150281851 | HEARING AID - A hearing aid includes at least two magnetic sensors, and the arrangements thereof are not parallel to each other so that the magnetic field can be detected more precisely to generate a clearer sound signal. Furthermore, the hearing aid can switch between two different receiving states according to different ways of generating sound signals, wherein the first receiving state generates a sound signal through the detection of the magnetic field and the second receiving state generates a sound signal through a microphone receiving sounds. | 10-01-2015 |
20150281858 | METHOD OF PROCESSING VOICE SIGNAL OUTPUT AND EARPHONE - A method of processing a voice output signal is applied in an earphone. The method processes the voice signal received from the earphone via a sound processing module inside the earphone such that a user can hear the voice signal more clearly. The earphone can be used as a hearing-aid when the user is not using a phone, and the earphone also can be used to help the user hear voice signals for phone communication. | 10-01-2015 |
Rex Young, Hsinchu City TW
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20080224202 | NON-VOLATILE MEMORY - A non-volatile memory includes a substrate, a number of isolation layers, a number of active layers, a number of floating gates, a number of control gates and a number of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the active layer is higher than that of the isolation layer. The active layers and the isolation layers are arranged in parallel to each other and extend in the first direction. The control gates are disposed in the substrate. The control gates are arranged in parallel and extend in the second direction which crosses the first direction. The floating gates are disposed between the active layers and the control gates. The doped regions are disposed in the active layers between the control gates. | 09-18-2008 |
20090075443 | METHOD OF FABRICATING FLASH MEMORY - A method of fabricating a flash memory includes providing a substrate with a mask layer thereon, forming pluralities of shallow trenches in the substrate, forming a first oxide layer on the substrate and in the shallow trenches, removing a portion of the first oxide layer above the mask layer, forming a second oxide layer on the mask layer and the first oxide layer, wherein the first and second oxide layers have different etching ratios, removing a portion of the second oxide layer positioned above the mask layer so that an STI is formed with the first and the second oxide layers in each shallow trench, removing the mask layer to form recess portions between adjacent STIs, and filling the recess portions with a conductive layer to form floating gates in the recess portions. | 03-19-2009 |
20090130808 | METHOD OF FABRICATING FLASH MEMORY - A method of fabricating a flash memory includes successively forming a floating gate insulating layer, a floating gate material layer, a dielectric layer, a control gate material layer, a silicide layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer, removing portions of the silicide layer, the control gate material layer, the dielectric layer, and the floating gate material layer not covered by the hard mask layer to form a stacked structure, forming a silicon cap layer covering the surface of the stacked structure, and performing a thermal process. | 05-21-2009 |
San-Lin Young, Taichung City TW
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20110196635 | CONTACTLESS SENSING DEVICE - A contactless sensing device comprises a magnetic stripe fixed on a tested object, a detector and a processor. The magnetic stripe has arranged plurality of N-pole and S-pole blocks. The detector includes a fixed magnetic layer with fixed magnetic direction, a free magnetic layer with changeable magnetic direction influenced by external magnetic field, and an insulating layer separated the fixed magnetic layer from the free magnetic layer. While the object is moving to make the magnetic stripe pass through the detector, the magnetic direction of the free magnetic layer is influenced by the N-pole and S-pole blocks, such that the magnetic direction of the free magnetic layer is parallel or anti-parallel to the fixed magnetic layer. The induced change of the magnetoresistance further result in the obvious change of the output signal to the processor, and then the information of the object is sensed and calculated from the processor. | 08-11-2011 |
Sea-Weng Young, Taipei County TW
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20080220623 | Connector and method thereof - The invention discloses a connector, which includes a first connecting unit, a second connecting unit, a third connecting unit, and a determining unit. Moreover, the first connecting unit is capable of being electrically connected to a first power source and/or a first data source; and the second connecting unit is capable of being electrically connected to a second power source and/or a second data source. Additionally, the determining unit is electrically connected to the first connecting unit and the second connecting unit respectively, for selectively outputting a data signal and/or a power signal based on a connecting status. Furthermore, the third connecting unit is electrically connected to the determining unit and an electronic device, for transmitting the data signal and/or the power signal from the determining unit to the electronic device. | 09-11-2008 |
20090256761 | HANDHELD DEVICE WITH SWITCHABLE SIGNAL RECEIVING MODES - A handheld device with switchable signal receiving modes includes a telescopic antenna, a telecommunication transceiver module, a satellite signal module, and a switch circuit. Upon receiving a switch signal, the switch circuit couples the telescopic antenna to the telecommunication transceiver module, and adjusts the telescopic antenna to a first length, so that the telecommunication transceiver module transmits and receives a signal of a first frequency, or the switch circuit adjusts the telescopic antenna to a second length, so that the telecommunication transceiver module transmits and receives a signal of a second frequency. Alternatively, the switch circuit couples the telescopic antenna to the satellite signal module, and adjusts the telescopic antenna to the second length, so that the satellite signal module receives a satellite signal. Thereby, the handheld device can receive signals of various frequencies via one antenna, so that different functional modules transmit and receive signals of different frequencies. | 10-15-2009 |
20090257203 | MOBILE COMMUNICATION DEVICE WITH REPLACEABLE FUNCTIONAL MODULES - A mobile communication device with replaceable function modules includes a main body and an externally connected device. The main body serves as a central member, and has a main hybrid joint including an electrical contact and a magnetic joint. The main hybrid joint of the main body is joined to a device hybrid joint of the externally connected device, so as to realize the function thereof. When joined together, the main body activates a functional module of the externally connected device functional module. In addition, the main body and the externally connected device are further joined through the magnetic joints. Therefore, when separated by accidentally falling onto the ground, the mobile communication device can be rejoined through the magnetic joints, and thus it is unnecessary to worry about the unavailability due to the break-down of the joint portion. | 10-15-2009 |
20090273319 | HANDHELD DEVICE WITH FAST-CHARGING CAPABILITY - A handheld device with a fast-charging capability is adapted to be connected to a charger to obtain an electric power. The handheld device includes a battery, a charging circuit, a safety circuit, a control unit, and an input module. The charging circuit is electrically connected to the charger and transfers an electric power to the battery. The safety circuit is used for restricting an upper limit of the electric power transferred by the charging circuit. The input module is provided for a user to input an emergency charge command. Upon receiving the emergency charge command, the control unit instructs the safety circuit to lower the restriction on the charging circuit, so as to raise the upper limit of the electric power that can be obtained by the charging circuit, thereby accelerating the charging of the battery. | 11-05-2009 |
Sea-Weng Young, Taipei TW
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20080293457 | Mobile phone - A mobile phone includes a housing and a keypad module. The keypad module is mounted detachably on the housing. The keypad module is double-sided and has a first user interface and a second user interface formed on two corresponding sides for providing operations different from each other. | 11-27-2008 |
Sheng-Tai Young, Hsinchu County TW
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20150138869 | NON-VOLATILE MEMORY - A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a second input terminal connected to the second word line, and an output terminal connected to the control line. The first cell has a control terminal connected to the first word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. The second cell has a control terminal connected to the second word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. | 05-21-2015 |
Shuenn-Tsong Young, Taipei City TW
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20090105574 | MAGNETIC ELECTRODE DEVICE AND AN ELECTROCARDIOGRAPH DETECTING METHOD THEREOF - A magnetic electrode device and it further provides a method of CEG detection and record by the use of the said electrode device. | 04-23-2009 |
Shuenn-Tsong Young, Hsinchu TW
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20100235747 | METHOD FOR ADJUSTING PARAMETERS OF AUDIO DEVICE - A method for adjusting parameters of an audio device is provided and applied to an adjusting system operated by a user to adjust the audio device. The method includes steps of: executing an application program with the adjusting system; the application program providing a graphical user interface for receiving data wherein the graphical user interface at least includes a plurality of options to be selected; and adjusting a plurality of parameters of the audio device associated with a first option when the first option of the plurality options is selected and outputting a sound by the audio device. | 09-16-2010 |
20130294626 | HEARING AID SYSTEM - A hearing aid system in communication with an adjusting apparatus which executes a fitting software is provided. The hearing aid system includes a hearing aid and an embedded integrated device. The hearing aid stores therein a first setting and is worn by the user. The user inputs setting data via the executed fitting software. The embedded integrated device receives the setting data from the electronic apparatus to program the hearing aid to change a first setting preciously stored in the hearing aid into a second setting associated with the setting data. | 11-07-2013 |
Shuenn-Tsong Young, Taipei TW
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20090137914 | PORTABLE HYDRAULIC SPHYGMOMANOMETER - The present invention provides a portable hydraulic sphygmomanometer comprising: a manual hydraulic belt, a pressure sensor for detecting the pressure of hydraulic belt, and a compute device for calculating the blood pressure. | 05-28-2009 |
Shuenn-Tsong Young, Hsinchu County TW
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20100284556 | HEARING AID SYSTEM - A hearing aid system in communication with an adjusting apparatus which executes a fitting software is provided. The hearing aid system includes a hearing aid and an integrated remote controller. The hearing aid stores therein a first setting and is worn by the user. The user inputs setting data via the executed fitting software. The integrated remote controller receives the setting data from the adjusting apparatus to program the hearing aid by changing the first setting into a second setting associated with the setting data. The integrated remote controller also controls the operation of the hearing aid. | 11-11-2010 |
20110021883 | Remote health care system for enabling user to select a symptom diagnosis algorithm appropriate to his/her individual disease and method thereof - This invention relates to a remote health care system and a method thereof for allowing medical experts specializing in various medical fields to upload various developed program files of symptom diagnosis algorithms to a database of a care server in the remote health care system for adding, revising or updating the program files stored therein, so that the care server can provide a variety of new and useful program files to a user and allow the user to select the program files more appropriate to his/her individual disease and to upload his/her physiological parameter data to the care server. Then, the care server can execute corresponding calculating and analyzing procedures to the uploaded physiological parameter data by using the symptom diagnosis algorithm in the selected program file, and transmit calculation and analysis results to the user or health care workers for precisely and objectively understand the user's individual physiological condition. | 01-27-2011 |
20110046971 | Remote healthcare method for measuring physiological parameter and reporting self-perceived health status - A remote healthcare method is applied to a healthcare server and includes the steps of receiving detected information from a physiological parameter detecting instrument, reading a patient identification code and a physiological parameter from the detected information, reading an identification datum and a medical history datum matched with the patient identification code from a history database according to the identification code, reading a disease matched with the disease classification code and a corresponding pathological symptom from the disease database according to at least one disease classification code in the medical history data, screening a corresponding matched pathological symptom from the pathological symptoms according to the read physiological parameter to create a self-perceived list, transmitting the self-perceived list to the physiological parameter detecting instrument, and waiting for a receipt of the selected option of the pathological symptom for determining an appropriate medical dosage or medical tool. | 02-24-2011 |
Tai-Homg Young, Taipei City TW
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20140371528 | ENDOSCOPE AND A METHOD FOR CHEMICAL MODIFICATION OF THE MEMBERS THEREOF - An endoscope and a method for chemical modification of the members thereof are provided, on one hand, a transparent isolation film is utilized such that the tissue fluid inside a subject cannot stick to a lens of the endoscope to maintain the optimal image capturing status of the lens of the endoscope without the need to extract the endoscope frequently from the body of the subject, such that not only the time consumed in the examination process may be reduced, but also the uncomfortable feeling of the subject in the examination process may be decreased; on the other hand, a chemical modification method for members of the endoscope is provided to reduce the negative impact on the lens of the endoscope resulted from liquid pollutant or mist, moisture. | 12-18-2014 |
Tai-Horng Young, Taipei City TW
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20140163102 | MEDICAL DRESSING FOR RESPIRATORY EPITHELIAL CELLS - The present invention provides a medical dressing for respiratory epithelial cells comprising a biocompatible polymer and retinoic acid, wherein, based on total volume of the dressing, the polymer is 99% or more, and retinoic acid is 1% or less. | 06-12-2014 |
Tai-Horng Young, Taipei TW
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20150105708 | STRAP STICKER FOR BODY ADHESION - A strap sticker for body adhesion is provided with an outer layer and an inner layer of different elastic coefficients, and an observation well running through both the inner layer and the outer layer, a well cross section profile of the observation well and a level for inner layer material coming out from the observation well changing with a force bearing status of a body of the strap sticker. Thereby, naked eyes may be used to identify directly a force bearing extension level of the strap sticker to meet the purpose of home use. | 04-16-2015 |
20160022878 | METHOD OF TREATING PLEURAL ABNORMALITY - The invention relates to a method of treating pleural abnormalities in a subject in need thereof, comprising the steps of: (a) attaching a biodegradable polymeric membrane onto a pleural wound to elicit fibronectin from fibroblasts to cause fibrous adhesion; and (b) securing the membrane with securement products, including sutures, staples, and sealants. The present invention also relates to a biodegradable adhesion membrane used for treating pleural abnormalities, comprising: a biodegradable base material selected from the group consisting of polycaprolactone (PCL), polylactic acid or polylactide (PLA), polyhydroxybutyrate (PHB), poly(ethylene adipate), poly(butylene adipate) (PBA), chitosan, hyaluronic acid, and polyglycolic acid (PGA); wherein the thickness of the membrane is 0.1-1 mm. | 01-28-2016 |
Ting-Jung Young, Taipei City TW
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20150248335 | NETWORK DEVICE AND OPERATING METHOD THEREOF - An operating method of a backup device includes displaying a window corresponding to a backup destination on a graphic user interface (GUI); under a condition that an add-into-backup-list command is received via the GUI, recording a first backup entry corresponding to backup target data by a backup list according to the add-into-backup-list command; after the first backup entry is recorded, displaying an icon corresponding to the first backup entry in the window corresponding to the backup destination; and under a condition that a start-backup command is received via the GUI, backing up the backup target data into the backup destination according to the start-backup command. | 09-03-2015 |
Tonho Young, Taipei County TW
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20140038921 | NEW LOW SIDE EFFECT PHARMACEUTICAL COMPOSITION CONTAINING ANTITUBERCULOSIS DRUGS - A pharmaceutical composition for treating tuberculotic diseases with no side effect/low side effect is provided by the present invention, which pharmaceutically effective amount of one or more compounds chosen from isoniazid, rifampin, pyrazinamide and ethambutol, and pharmaceutically effective amount of substances which can reduce the side effect of the antituberculosis agents. | 02-06-2014 |
Ton Ho Young, Taipei TW
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20110207684 | NEW LOW SIDE EFFECT PHARMACEUTICAL COMPOSITION CONTAINING ISONIAZID - The present invention features a novel, low side-effect pharmaceutical compound complex, comprising the pharmaceutically effective dose of isoniazid (INH) and pharmaceutically effective dose of one of the following compounds. Said compound was selected from the following groups of compounds: Nordihydroguaiaretic acid, Trans-Cinnamaldehyde, Daidzein, Isovitexin, Kaempferol, disulfuram, β-Myrcene, Quercetin, (−)-Epigallocatechin-3-gallate, (+)-Limonene, Myricetin, Quercitrin, Luteolin-7-Glucoside, Morin, Neohesperidin, Hesperidin, Capillarisin, (−)-Epigallocatechin, Luteolin, Hyperoside, Ethyl Myristate, Tamarixetin, Phloretin, Baicalein, Rutin, Baicalin, Apigenin, Naringenin, Hesperetin, (+)-Epicatechin, (−)-Epicatechin-3-gallat, Isoliquritigenin, Silybin, Vitexin, Genistein, Isorhamnetin, gallic acid, Diosmin, 6-Gingerol, (+)-Taxifolin, Wongonin, Protocatechuic acid, (+)-Catechin, β-naphthoflavone, Embelin, Trans-Cinnamic acid, (−)-Epicatechin, Phloridzin, Puerarin, Umbelliferone, Brij 58, Brij 76, Brij 35, Tween 20, Tween 80, Tween 40, PEG 2000, PEG 400, Pluornic F68, and PEG 4000. The novel, low side-effect compound complex which contains pharmaceutically effective doses of isoniazid (INH), disulfuram (DSF) and/or a third compound, bis-nitrophenyl phosphate (BNPP) can reduce isoniazid (INH)-induced side effects, e.g. hepatotoxicity, etc. | 08-25-2011 |
Whu-Ming Young, Taipei TW
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20120306390 | Architecture for Supporting Modulized Full Operation Junction Ultra High Voltage (UHV) Light Emitting Diode (LED) Device - The present disclosure provides an ultra high voltage (UHV) light emitting diode (LED) device. According to one embodiment, the device includes a substrate, a plurality of LED junctions disposed above the substrate and coupled to one another, and a control component including a plurality of switches embedded within the substrate and coupled to the plurality of LED junctions to control routing of current across the plurality of LED junctions. | 12-06-2012 |
20120306392 | LIGHT-EMITTING DIODE NETWORK - LED devices or circuits include a number of serially connected LED segments, which may additionally include parallel branches, which are switched on or off depending on an input voltage to the LED segments. As the input voltage varies, none, different portions, or all of the LEDs are lit. The input voltage to the LED segments may be an output voltage from a bridge rectifier in response to an alternate current (AC) power. The LED devices or circuits include no inductors, transformers and electrolytic capacitors. | 12-06-2012 |
Yao-Ming Young, Chungli City TW
Patent application number | Description | Published |
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20090094811 | FRONT RELEASE BUCKLE - A front release buckle includes a female buckle member, which has a hooked portion at the front side of a top-open receiving chamber thereof, a male buckle member, which has a front hook vertically insertable into the top-open receiving open chamber into engagement with the hooked portion of the female buckle member, a control slide coupled to the female buckle member and movable relative to the female buckle member between an open position to open the top-open receiving chamber for the insertion of the front hook of the male buckle member into engagement with the hooked portion and a close position to close the top-open receiving chamber and to hold down the front hook of the male buckle member after engagement of the front hook with the hooked portion, and a spring member that supports the control slide in the close position. | 04-16-2009 |
Yi Foung Young, Yilan County TW
Patent application number | Description | Published |
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20100282205 | INFRARED COMPLEX AND A VEHICLE POWER IMPROVING SYSTEM USING THE INFRARED COMPLEX - An infrared complex and a vehicle power improving system using the infrared complex are disclosed. The infrared complex is made by an infrared material and a composite material that is coated on the infrared material. The vehicle power improving system comprises at least an element for increasing oxygen content that is fixed in the air intake line of a vehicle engine, at least a first element for reducing oxidized fuel oil and covering the fuel oil intake line of the vehicle engine, at least a second element attached to a shock absorber of the vehicle for restoring deformed shock oil molecules in the shock absorber, and a voltage stabilizer electrically connected with the battery and the generator of the vehicle. Thereby, it is able to increase the oxygen content of the air flowing into the vehicle engine and to reduce the oxidized oil in the fuel oil intake line, so that the utility efficiency of fuel oil can be enhanced and the amount of waste exhaust gas can be reduced. | 11-11-2010 |
Zhi-Huei Young, Taipei TW
Patent application number | Description | Published |
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20090045243 | Butt welding and feeding machine - Rolls of steel plates fed to a butt welding and feeding machine, a seamless welding between two adjoining juxtaposed steel plates must be first trimming off both butt ends or leading and trailing edge flanges. After trimming, the trimmed leading and trailing edges flush against each other. Welding torch opposite to a junction line moves along a transversal rail to weld two adjoining juxtaposed steel plates together. Preceding and following steel plates are fed with precision throughout both feeding, discharging rollers driven by servo motors. Steel plate held by a number of jaws urged by springs can reduce inner stress or friction happened between the steel plates; in addition, a gas cutting, machine for trimming off the butt ends, trimmed leading and trailing edges facilitate welding more promptly and efficiently. A good shelf at a front end of the machine can facilitate storing and fixing rolls of steel coil. | 02-19-2009 |