Patent application number | Description | Published |
20110055526 | METHOD AND APPARATUS FOR ACCESSING MEMORY ACCORDING TO PROCESSOR INSTRUCTION - There is provided a method and apparatus for accessing a memory according to a processor instruction. The apparatus includes: a stack offset extractor extracting an offset value from a stack pointer offset indicating a local variable in the processor instruction; a local stack storage including a plurality of items, each of which is formed of an activation bit indicating whether each item is activated, an offset storing an offset value of a stack pointer, and an element storing a local variable value of the stack pointer; an offset comparator comparing the extracted offset value with an offset value of each item and determining whether an item corresponding to the extracted offset value is present in the local stack storage; and a stack access controller controlling a processor to access the local stack storage or a cache memory according to a determining result of the offset comparator. | 03-03-2011 |
20110099334 | CORE CLUSTER, ENERGY SCALABLE VECTOR PROCESSING APPARATUS AND METHOD OF VECTOR PROCESSING INCLUDING THE SAME - A core cluster includes a cache memory, a core, and a cluster cache controller. The cache memory stores and provides instructions and data. The core accesses the cache memory or a cache memory provided in an adjacent core cluster, and performs an operation. The cluster cache controller allows the core to access the cache memory when the core requests memory access. The cluster cache controller allows the core to access the cache memory provided in the adjacent core cluster when the core requests a clustering to the adjacent core cluster. The cluster cache controller allows a core provided in the adjacent core cluster to access the cache memory when the core receives a clustering request from the adjacent core cluster. | 04-28-2011 |
20110107063 | VECTOR PROCESSING APPARATUS AND METHOD - There is provided a vector processing apparatus and method allowing for the parallel processing of a plurality of different instructions while maintaining vector processing architecture. The vector processing apparatus includes an instruction memory storing a multiple instruction group including one or more instructions; an instruction fetch unit reading the multiple instruction group from the instruction memory; and a plurality of instruction processing units each receiving the multiple instruction group through the instruction fetch unit, selecting a single instruction from the multiple instruction group according to a previous arithmetic result, and performing a arithmetic operation. | 05-05-2011 |
20120117357 | ENERGY TILE PROCESSOR - An energy tile processor in which an internal structure of a single processor is divided into a part for supplying instructions and another part for executing the instructions in order for operating voltages and operating frequencies to be supplied independently. The processor includes an instruction supply unit storing instructions and issuing instructions to be executed, a first execution unit executing an integer operation and a memory operation according to an operation type of the instruction issued by the instruction supply unit, and a second execution unit executing a floating point operation according to an operation type of the instruction issued by the instruction supply unit. The instruction supply unit, the first execution unit, and the second execution unit are driven at operating voltages and operating frequencies which are independently controlled. | 05-10-2012 |
20130080747 | PROCESSOR AND INSTRUCTION PROCESSING METHOD IN PROCESSOR - The present invention relates to a processor including: an instruction cache configured to store at least some of first instructions stored in an external memory and second instructions each including a plurality of micro instructions; a micro cache configured to store third instructions corresponding to the plurality of micro instructions included in the second instructions; and a core configured to read out the first and second instructions from the instruction cache and perform calculation, in which the core performs calculation by the first instructions from the instruction cache under a normal mode, and when the process enters a micro instruction mode, the core performs calculation by the third instructions corresponding to the plurality of micro instructions provided from the micro cache. | 03-28-2013 |
20140025894 | PROCESSOR USING BRANCH INSTRUCTION EXECUTION CACHE AND METHOD OF OPERATING THE SAME - A processor using a branch instruction execution cache and a method of operating the same are disclosed. The processor according to an example embodiment of the present invention includes a fetch unit, a branch prediction unit, an instruction queue, a decoding unit and an execution unit operating in a pipeline manner, and includes a branch instruction execution cache that stores address and decode information of a transferred instruction output from the decoding unit, and provides the stored address and at least some of pieces of the decode information to the execution unit in order to overcome branch misprediction when the execution unit determines the branch misprediction. Therefore, with the processor according to an example embodiment of the present invention, overhead of pipeline initialization can be minimized to prevent performance degradation of the processor and reduce power consumption of the processor. | 01-23-2014 |
20140344551 | DUAL-MODE INSTRUCTION FETCHING APPARATUS AND METHOD - The dual-mode instruction fetching apparatus includes a mode register, a branch prediction unit, a Program Counter (PC) calculator, an Instruction Queue (IQ), and a fetch multiplexer. The mode register is set to one of normal mode and line mode. The PC calculator accesses a tag in which the address indices of instructions have been stored or a line in which the instructions have been grouped and then outputs an instruction, or accesses only the line and then outputs an instruction depending on the type of set mode. The IQ stores instructions selected by an instruction selector from among the instructions grouped in the line. The fetch multiplexer fetches the instructions stored in the IQ if the normal mode has been set, and fetches instructions read from the line of an instruction cache if the line mode has been set. | 11-20-2014 |
20140344619 | PROCESSOR CAPABLE OF DETECTING FAULT AND METHOD OF DETECTING FAULT OF PROCESSOR CORE USING THE SAME - A processor capable of detecting fault and a method of detecting the fault of processor core using the same are disclosed. The processor includes a first processor core, a second processor core, and a fault manager. The first processor core includes one or more pipeline registers. The second processor core has a same structure as the first processor core, and is included in a single chip along with the first processor core. The comparator compares the value of the pipeline register of the first processor core with the value of the pipeline register of the second processor core. The fault manager performs a fault management operation if, as a result of the comparison of the comparator, it is determined that a fault has occurred. | 11-20-2014 |
20140359316 | METHOD AND APPARATUS FOR CONTROLLING OPERATION VOLTAGE OF PROCESSOR CORE, AND PROCESSOR SYSTEM INCLUDING THE SAME - A method and an apparatus for controlling an operation voltage of a processor core and a processor system including the same are provided. The apparatus for controlling an operation voltage of a processor core includes a voltage supplier and an operation voltage searching core. The voltage supplier supplies the operation voltage to the processor core. The operation voltage searching core requests the processor core to execute a program, and controls the operation voltage based on whether the program has been normally operated. | 12-04-2014 |