Patent application number | Description | Published |
20080197350 | Thin film transistor and method of forming the same - A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer. | 08-21-2008 |
20080203387 | Thin film transistor and method of manufacturing the same - Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain. The metal oxide layer may have a gradually changing metal content between the channel layer and the source and the drain. | 08-28-2008 |
20080224269 | Gettering structures and methods and their application - An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation. | 09-18-2008 |
20080237687 | Flash memory device - Provided is a flash memory device including a gate structure on a substrate. The flash memory device includes a charge supply layer including a ZnO based material formed between a substrate and a gate structure or formed on the gate structure. Accordingly, the flash memory device can be formed to be of a bottom gate type or of a top gate type by including the charge supply layer. Also, the flash memory device may be realized to be any of a charge trap type and a floating gate type. | 10-02-2008 |
20080246077 | Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method - In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure. | 10-09-2008 |
20080258141 | Thin film transistor, method of manufacturing the same, and flat panel display having the same - A thin film transistor (TFT), a method of manufacturing the TFT, and a flat panel display comprising the TFT are provided. The TFT includes a gate, a gate insulating layer that contacts the gate, a channel layer that contacts the gate insulating layer and faces the gate with the gate insulating layer therebetween, a source that contacts an end of the channel layer; and a drain that contacts an other end of the channel layer, wherein the channel layer is an amorphous oxide semiconductor layer, and each of the source and the drain is a conductive oxide layer comprising an oxide semiconductor layer having a conductive impurity in the oxide semiconductor layer. A low resistance metal layer can further be included on the source and drain. A driving circuit of a unit pixel of a flat panel display includes the TFT. | 10-23-2008 |
20080278989 | Resistive memory device and method of manufacturing the same - Provided is a resistive memory device and a method of manufacturing the resistive memory device that includes a bottom electrode, an insulating layer that is formed on the bottom electrode and has a hole that exposes the bottom electrode, a resistance layer and an intermediate layer which are formed in the hole, a switch structure formed on a surface of the intermediate layer, and an upper electrode formed on the switch structure. | 11-13-2008 |
20080296550 | Resistive random access memory device and methods of manufacturing and operating the same - Provided may be a resistive random access memory (RRAM) device and methods of manufacturing and operating the same. The resistive random access memory device may include at least one first electrode, at least one second electrode spaced apart from the at least one first electrode, a first structure including a first resistance-changing layer between the at least one first and second electrodes, and a first switching element electrically connected to the first resistance-changing layer, wherein at least one of the first and second electrodes include an alloy layer having a noble metal and a base metal. | 12-04-2008 |
20080308783 | Memory devices and methods of manufacturing the same - Memory devices and methods of manufacturing the same are provided. In a memory device, a memory-switch structure is formed between a first and second electrode. The memory-switch structure includes a memory resistor and a switch structure. The switch structure controls current supplied to the memory resistor. A memory region of the memory resistor and a switch region of the switch structure are different from each other. | 12-18-2008 |
20080315193 | Oxide-based thin film transistor, method of fabricating the same, zinc oxide etchant, and a method of forming the same - Provided is a zinc (Zn) oxide-based thin film transistor that may include a gate, a gate insulating layer on the gate, a channel including zinc oxide and may be on a portion of the gate insulating layer, and a source and drain contacting respective sides of the channel. The zinc (Zn) oxide-based thin film transistor may further include a recession in the channel between the source and the drain, and a zinc oxide-based etchant may be used to form the recession. | 12-25-2008 |
20080315200 | Oxide semiconductors and thin film transistors comprising the same - Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Hf and Cr atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Hf and Cr atoms added thereto. | 12-25-2008 |
20090001432 | Channel layer for a thin film transistor, thin film transistor including the same, and methods of manufacturing the same - Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer. | 01-01-2009 |
20090003062 | Non-volatile semiconductor device - A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size. | 01-01-2009 |
20090008638 | Oxide semiconductor, thin film transistor including the same and method of manufacturing a thin film transistor - Example embodiments relate to an oxide semiconductor including zinc oxide (ZnO), a thin film transistor including a channel formed of the oxide semiconductor and a method of manufacturing the thin film transistor. The oxide semiconductor may include a Ga | 01-08-2009 |
20090045429 | Diode structure and memory device including the same - Provided are a diode structure and a memory device including the same. The diode structure includes: a first electrode; a p-type Cu oxide layer formed on the first electrode; an n-type InZn oxide layer formed on the p-type Cu oxide layer; and a second electrode formed on the n-type InZn oxide. | 02-19-2009 |
20090057663 | Oxide thin film transistor and method of manufacturing the same - An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer. | 03-05-2009 |
20090057745 | Inverted nonvolatile memory device, stack module, and method of fabricating the same - Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer. | 03-05-2009 |
20090072246 | Diode and memory device comprising the same - Provided are a diode and a memory device comprising the diode. The diode includes a p-type semiconductor layer and an n-type semiconductor layer, wherein at least one of the p-type semiconductor layer and the n-type semiconductor layer comprises a resistance changing material whose resistance is changed according to a voltage applied to the resistance changing material. | 03-19-2009 |
20090086527 | Non-volatile memory device having threshold switching resistor, memory array including the non-volatile memory device and methods of manufacturing the same - Provided are a non-volatile memory device having a threshold switching resistor, a memory array including the non-volatile memory device, and methods of manufacturing the same. A non-volatile memory device having a threshold switching resistor may include a first resistor having threshold switching characteristics, an intermediate electrode on the first resistor, and a second resistor having at least two resistance characteristics on the intermediate electrode. | 04-02-2009 |
20090095985 | Multi-layer electrode, cross point memory array and method of manufacturing the same - Provided may be a multi-layer electrode, a cross point resistive memory array and method of manufacturing the same. The array may include a plurality of first electrode lines arranged parallel to each other; a plurality of second electrode lines crossing the first electrode lines and arranged parallel to each other; and a first memory resistor at intersections between the first electrode lines and the second electrode lines, wherein at least one of the first electrode lines and the second electrode lines have a multi-layer structure including a first conductive layer and a second conductive layer formed of a noble metal. | 04-16-2009 |
20090101948 | CMOS image sensors having transparent transistors and methods of manufacturing the same - CMOS image sensors having transparent transistors and methods of manufacturing the same are provided. The CMOS image sensors include a photodiode and at least one transistor formed on the photodiode. The image sensor may include a plurality of transistors wherein at least one of the plurality of transistors is a transparent transistor. | 04-23-2009 |
20090116272 | Non-volatile memory device including diode-storage node and cross-point memory array including the non-volatile memory device - Provided are a non-volatile memory device and a cross-point memory array including the same which have a diode characteristic enabling the non-volatile memory device and the cross-point memory array including the same to operate in a simple structure, without requiring a switching device separately formed so as to embody a high density non-volatile memory device. The non-volatile memory device includes a first electrode; a diode-storage node formed on the first electrode; and a second electrode formed on the diode-storage node. | 05-07-2009 |
20090146142 | Light-emitting device including nanorod and method of manufacturing the same - Provided are a light-emitting device including a plurality of nanorods each of which comprises an active layer formed between an n-type region and a p-type region, and a method of manufacturing the same. The light-emitting device comprises: a substrate; a first electrode layer formed on the substrate; a basal layer formed on the first electrode layer; a plurality of nanorods formed vertically on the basal layer, each of which comprises a bottom part doped with first type, a top part doped with second type opposite to the first type, and an active layer between the bottom part and the top part, an insulating region formed between the nanorods, and a second electrode layer formed on the nanorods and the insulating region. | 06-11-2009 |
20090243115 | Semiconductor device and method of manufacturing the same - Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array and the peripheral circuit are electrically connected to each other. | 10-01-2009 |
20090296621 | INFORMATION SERVICE APPARATUS AND METHOD IN WIRELESS COMMUNICATION SYSTEM - An information service apparatus and method in a wireless communication system are provided. A method of operating a Radio Access Station (RAS) includes receiving information regarding business offices located in a cell coverage area of the RAS from a network entity of a core service network, classifying the received business office information according to a plurality of items and storing the classified information in a Data Base (DB), allocating a Multicast Connection IDentifier (MCID) for each item, determining a transmission period for each item, obtaining a business office list of a corresponding item from the DB when a Transmit (Tx) time elapses according to the Tx period, generating an advertisement multicast burst including the obtained business office list, and multicasting the generated burst to pre-registered Mobile Stations (MSs). | 12-03-2009 |
20100059750 | BOTTOM GATE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region. | 03-11-2010 |
20100091541 | Stacked memory device and method thereof - A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit. | 04-15-2010 |
20100123158 | Light emitting device and method of manufacturing the same - Provided is a light emitting diode (LED) manufactured by using a wafer bonding method and a method of manufacturing a LED by using a wafer bonding method. The wafer bonding method may include interposing a stress relaxation layer formed of a metal between a semiconductor layer and a bonding substrate. When the stress relaxation layer is used, stress between the bonding substrate and a growth substrate may be offset due to the flexibility of metal, and accordingly, bending or warpage of the bonding substrate may be reduced or prevented. | 05-20-2010 |
20100124798 | Method of manufacturing light emitting device - Provided is a method of manufacturing a light emitting device from a large-area bonding wafer by using a wafer bonding method using. The method may include forming a plurality of semiconductor layers, each having an active region for emitting light, on a plurality of growth substrates. The method may also include arranging the plurality of growth substrates on which the semiconductor layers are formed on one bonding substrate and simultaneously processing each of the semiconductor layers formed on each of the growth substrates through subsequent processes. The bonding wafer may be formed of a material that reduces or prevents bending or warping due to a difference of thermal expansion coefficients between a wafer material, such as sapphire, and a bonding wafer. According to the above method, because a plurality of wafers may be processed by one process, mass production of LEDs may be possible which may reduce manufacturing costs. | 05-20-2010 |
20100135059 | Information storage devices using magnetic domain wall movement and methods of operating the same - Provided are information storage devices using movement of magnetic domain walls and methods of operating information storage devices. An information storage device includes a magnetic track and an operating unit. The magnetic track includes a plurality of magnetic domains separated by magnetic domain walls. The size of the operating unit is sufficient to cover at least two adjacent magnetic domains. And, the operating unit may be configured to write/read information to/from a single magnetic domain as well as a plurality of magnetic domains of the magnetic track. | 06-03-2010 |
20100148825 | Semiconductor devices and methods of fabricating the same - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device. | 06-17-2010 |
20100208368 | Microlens, an image sensor including a microlens, method of forming a microlens and method for manufacturing an image sensor - A microlens, an image sensor including the microlens, a method of forming the microlens and a method of manufacturing the image sensor are provided. The microlens includes a polysilicon pattern, having a cylindrical shape, formed on a substrate, and a round-type shell portion enclosing the polysilicon pattern. The microlens may further include a filler material filling an interior of the shell portion, or a second shell portion covering the first shell portion. The method of forming a microlens includes forming a silicon pattern on a semiconductor substrate having a lower structure, forming a capping film on the semiconductor substrate over the silicon pattern, annealing the silicon pattern and the capping film altering the silicon pattern to a polysilicon pattern having a cylindrical shape and the capping film to a shell portion for a round-type microlens, and filling an interior of the shell portion with a lens material through an opening between the semiconductor substrate and an edge of the shell portion. The image sensor includes a microlens formed by a similar method and a photodiode having a cylindrical shape. | 08-19-2010 |
20100233869 | METHOD OF FABRICATING EPI-WAFER, EPI-WAFER FABRICATED BY THE METHOD, AND IMAGE SENSOR FABRICATED USING THE EPI-WAFER - A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one surface of the wafer, performing thermal treatment of the wafer, removing the insulating layer formed on one surface of the wafer, mirror-surface-grinding one surface of the wafer, and growing an epitaxial layer on one surface of the wafer and forming a high-density boron layer within the wafer that corresponds to the interface between the wafer and the epitaxial layer. | 09-16-2010 |
20100308297 | Heterojunction diode, method of manufacturing the same, and electronic device including the heterojunction diode - Example embodiments relate to a heterojunction diode, a method of manufacturing the heterojunction diode, and an electronic device including the heterojunction diode. The heterojunction diode may include a first conductive type non-oxide layer and a second conductive type oxide layer bonded to the non-oxide layer. The non-oxide layer may be a Si layer. The Si layer may be a p++ Si layer or an n++ Si layer. A difference in work functions of the non-oxide layer and the oxide layer may be about 0.8-1.2 eV. Accordingly, when a forward voltage is applied to the heterojunction diode, rectification may occur. The heterojunction diode may be applied to an electronic device, e.g., a memory device. | 12-09-2010 |
20110001746 | Apparatuses for and methods of displaying three-dimensional images - An apparatus for displaying a three-dimensional (3D) image may include a plurality of display panels and a controller configured to apply image signals to each of the plurality of display panels. At least one of the display panels may include a transparent display panel. The plurality of display panels may be spaced apart from each other in a depth direction. A method of displaying a three-dimensional (3D) image may include displaying plane images on each of a plurality of display panels. At least one of the plurality of display panels may include a transparent display panel. The plurality of display panels may be spaced apart from each other in a depth direction. | 01-06-2011 |
20110008920 | Microlens, an image sensor including a microlens, method of forming a microlens and method for manufacturing an image sensor - A microlens, an image sensor including the microlens, a method of forming the microlens and a method of manufacturing the image sensor are provided. The microlens includes a polysilicon pattern, having a cylindrical shape, formed on a substrate, and a round-type shell portion enclosing the polysilicon pattern. The microlens may further include a filler material filling an interior of the shell portion, or a second shell portion covering the first shell portion. The method of forming a microlens includes forming a silicon pattern on a semiconductor substrate having a lower structure, forming a capping film on the semiconductor substrate over the silicon pattern, annealing the silicon pattern and the capping film altering the silicon pattern to a polysilicon pattern having a cylindrical shape and the capping film to a shell portion for a round-type microlens, and filling an interior of the shell portion with a lens material through an opening between the semiconductor substrate and an edge of the shell portion. The image sensor includes a microlens formed by a similar method and a photodiode having a cylindrical shape. | 01-13-2011 |
20110042669 | Thin film transistors and methods of manufacturing the same - A transistor may include: a gate insulting layer, a gate electrode formed on a bottom side of the gate insulating layer, a channel layer formed on a top side of the gate insulating layer, a source electrode that contacts a first portion of the channel layer, and a drain electrode that contacts a second portion of the channel layer. The channel layer may have a double-layer structure, including an upper layer and a lower layer. The upper layer may have a carrier concentration lower than that of the lower layer. The upper layer may be doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer. | 02-24-2011 |
20110076838 | Gettering structures and methods and their application - An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation. | 03-31-2011 |
20110101342 | ZnO based semiconductor devices and methods of manufacturing the same - A semiconductor device may include a composite represented by Formula 1 below as an active layer. | 05-05-2011 |
20110101343 | ZnO based semiconductor devices and methods of manufacturing the same - A semiconductor device may include a composite represented by Formula 1 below as an active layer. | 05-05-2011 |
20110114915 | Light emitting device and method of fabricating the same - A light emitting device may include a plurality of nano-structures having a strip shape, each including a first nano-structure and a second nano-structure, the first nano-structures being the same height on the buffer layer. | 05-19-2011 |
20110141100 | Thin film transistor and method of forming the same - A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer. | 06-16-2011 |
20110175080 | Transistors, methods of manufacturing a transistor, and electronic devices including a transistor - Transistors, methods of manufacturing a transistor, and electronic devices including a transistor are provided, the transistor includes a channel layer, a source and a drain respectively contacting opposing ends of the channel layer, a gate corresponding to the channel layer, a gate insulating layer between the channel layer and the gate, and a first passivation layer and a second passivation layer sequentially disposed on the gate insulating layer. The first passivation layer covers the source, the drain, the gate, the gate insulating layer and the channel layer. The second passivation layer includes fluorine (F). | 07-21-2011 |
20110193940 | 3D CMOS Image Sensors, Sensor Systems Including the Same - A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto. | 08-11-2011 |
20110272712 | Vertical light-emitting devices having patterned emitting unit and methods of manufacturing the same - Example embodiments are directed to a light-emitting device including a patterned emitting unit and a method of manufacturing the light-emitting device. The light-emitting device includes a first electrode on a top of a semiconductor layer, and a second electrode on a bottom of the semiconductor layer, wherein the semiconductor layer is a pattern array formed of a plurality of stacks. A space between the plurality of stacks is filled with an insulating layer, and the first electrode is on the insulating layer. | 11-10-2011 |
20110291120 | Light Emitting Devices Using Connection Structures And Methods Of Manufacturing The Same - Example embodiments of the present invention relate to a light emitting device having a connection structure and a method of manufacturing the light emitting device. The method of manufacturing may include forming a light emitting region and electrode layers on a substrate in which a plurality of cell regions and a bridge for partially connecting the cell regions are disposed, thereby providing a light emitting device that controls stress with relative ease and integrates electrical connections between the cell regions. | 12-01-2011 |
20120018734 | Light-emitting devices and methods of manufacturing the same - Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer. | 01-26-2012 |
20120056304 | Wafer, Fabricating Method Of The Same, And Semiconductor Substrate - A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface. | 03-08-2012 |
20120074385 | Semiconductor Devices And Methods of Manufacturing The Same - A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer. | 03-29-2012 |
20120175662 | VERTICAL LIGHT EMITTING DEVICE - According to an example embodiment, a vertical light emitting device (LED) includes a semiconductor layer including an active layer configured to emitting light, a first electrode on a first side of the semiconductor layer, and a second electrode on a second side of the semiconductor layer opposite to the first electrode. At least one of the first and second electrodes includes a metal electrode pattern and a transparent electrode pattern. The transparent electrode pattern is in a region between segment electrodes of the metal electrode pattern. The transparent electrode pattern is electrically connected to the metal electrode pattern. | 07-12-2012 |
20120282734 | OXIDE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer. | 11-08-2012 |
20120295399 | OXIDE-BASED THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, ZINC OXIDE ETCHANT, AND A METHOD OF FORMING THE SAME - Provided is a zinc (Zn) oxide-based thin film transistor that may include a gate, a gate insulating layer on the gate, a channel including zinc oxide and may be on a portion of the gate insulating layer, and a source and drain contacting respective sides of the channel. The zinc (Zn) oxide-based thin film transistor may further include a recession in the channel between the source and the drain, and a zinc oxide-based etchant may be used to form the recession. | 11-22-2012 |
20130105840 | MULTI-PORT LIGHT SOURCES OF PHOTONIC INTEGRATED CIRCUITS | 05-02-2013 |
20130139966 | JIG FOR USE IN ETCHING AND CHEMICAL LIFT-OFF APPARATUS INCLUDING THE SAME - A jig for use in etching supports an etching target while an etching process is performed and surrounds a remaining region of the etching target except for a portion of the etching target, so as to expose the portion of the etching target. Accordingly, a stable support of the etching target during the etching process may be provided, and thus an etching of an undesired region may be prevented, and a stable production yield may be accomplished. | 06-06-2013 |
20130175541 | METHOD OF GROWING NITRIDE SEMICONDUCTOR LAYER - A method of growing a nitride semiconductor layer may include preparing a substrate in a reactor, growing a first nitride semiconductor on the substrate at a first temperature, the first nitride semiconductor having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate, and removing the substrate at a second temperature. | 07-11-2013 |
20130177323 | MICROPROCESSOR CHIP, DATA CENTER, AND COMPUTING SYSTEM - A microprocessor chip includes a plurality of processors; at least one first optical input/output unit configured to receive optical signals from an external device and transmit optical signals to the external device; and an optical system bus that is connected between the plurality of processors and the at least one first optical input/output unit. | 07-11-2013 |
20130188257 | MICRO LENS, DEVICE EMPLOYING THE SAME, AND METHOD OF MANUFACTURING THE SAME - Example embodiments relate to a micro lens and a method of manufacturing the micro lens. The micro lens may include a substrate and an internal lens region existing in the substrate. The internal lens region may have a refractive index that is different from a refractive index of the substrate. The internal lens region may include at least one boundary contacting the substrate and formed as a curve. As a result, light incident in the substrate through a surface of the substrate is converged or diverged by the curve. | 07-25-2013 |
20130188904 | HYBRID LASER LIGHT SOURCES FOR PHOTONIC INTEGRATED CIRCUITS - A light source for a photonic integrated circuit may comprise a reflection coupling layer formed on a substrate in which an optical waveguide is provided, at least one side of the reflection coupling layer being optically connected to the optical waveguide; an optical mode alignment layer provided on the reflection coupling layer; and/or an upper structure provided on the optical mode alignment layer and including an active layer for generating light and a reflection layer provided on the active layer. A light source for a photonic integrated circuit may comprise a lower reflection layer; an optical waveguide optically connected to the lower reflection layer; an optical mode alignment layer on the lower reflection layer; an active layer on the optical mode alignment layer; and/or an upper reflection layer on the active layer. | 07-25-2013 |
20130252395 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - Example embodiments relate to a resistive random access memory (RRAM) and a method of manufacturing the RRAM. A RRAM according to example embodiments may include a lower electrode, which may be formed on a lower structure (e.g., substrate). A resistive layer may be formed on the lower electrode, wherein the resistive layer may include a transition metal dopant. An upper electrode may be formed on the resistive layer. Accordingly, the transition metal dopant may form a filament in the resistive layer that operates as a current path. | 09-26-2013 |
20140057381 | VERTICAL LIGHT-EMITTING DEVICES HAVING PATTERNED EMITTING UNIT AND METHODS OF MANUFACTURING THE SAME - Example embodiments are directed to a light-emitting device including a patterned emitting unit and a method of manufacturing the light-emitting device. The light-emitting device includes a first electrode on a top of a semiconductor layer, and a second electrode on a bottom of the semiconductor layer, wherein the semiconductor layer is a pattern array formed of a plurality of stacks. A space between the plurality of stacks is filled with an insulating layer, and the first electrode is on the insulating layer. | 02-27-2014 |
20140073115 | METHOD OF MANUFACTURING LARGE AREA GALLIUM NITRIDE SUBSTRATE - A method of manufacturing a large area gallium nitride (GaN) substrate includes forming a buffer layer on a silicon substrate, forming an insulation layer pattern on a rim of a top surface of the buffer layer, growing a GaN layer on the buffer layer, and removing the insulation layer pattern and a portion of the GaN layer and the silicon substrate. | 03-13-2014 |
20140353677 | LOW-DEFECT SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a low-defect semiconductor device and a method of manufacturing the same. The method includes forming a buffer layer on a silicon substrate, forming an interface control layer on the buffer layer under a first growth condition, and forming a nitride stack on the interface control layer under a second growth condition different from the first growth condition. | 12-04-2014 |
20140363932 | ZINC TARGET INCLUDING FLUORINE, METHOD OF FABRICATING ZINC NITRIDE THIN FILM BY USING THE SAME, AND METHOD OF FABRICATING THIN FILM TRANSISTOR BY USING THE SAME - Provided are fluorine-containing zinc targets, methods of fabricating a zinc oxynitride thin film by using the zinc targets, and methods of fabricating a thin film transistor by using the zinc oxynitride thin film. The methods include mounting a fluorine-containing zinc target and a substrate in a sputtering chamber, supplying nitrogen gas and inert gas into the sputtering chamber, and forming a fluorine-containing zinc oxynitride thin film on the substrate. | 12-11-2014 |
20150028278 | NONVOLATILE MEMORY TRANSISTOR AND DEVICE INCLUDING THE SAME - Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic. | 01-29-2015 |
20150060762 | SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING HOLE INJECTION LAYER - According to example embodiments, a semiconductor light emitting device includes a first semiconductor layer, a pit enlarging layer on the first semiconductor layer, an active layer on the pit enlarging layer, a hole injection layer, and a second semiconductor layer on the hole injection layer. The first semiconductor layer is doped a first conductive type. An upper surface of the pit enlarging layer and side surfaces of the active layer define pits having sloped surfaces on the dislocations. The pits are reverse pyramidal spaces. The hole injection layer is on a top surface of the active layer and the sloped surfaces of the pits. The second semiconductor layer doped a second conductive type that is different than the first conductive type. | 03-05-2015 |