Patent application number | Description | Published |
20100091549 | Non-Volatile Memory Cell with Complementary Resistive Memory Elements - A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell. | 04-15-2010 |
20100110764 | PROGRAMMABLE METALLIZATION CELL SWITCH AND MEMORY UNITS CONTAINING THE SAME - An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel. | 05-06-2010 |
20100117160 | POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY - Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material. | 05-13-2010 |
20100124106 | MAGNETIC MEMORY WITH MAGNETIC TUNNEL JUNCTION CELL SETS - A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell set itself is configured to switch between a high resistance state and a low resistance state. The memory apparatus also has at least one reference cell set comprising a third spin torque memory cell electrically connected in anti-series to a fourth spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The reference cell set itself has a reference resistance that is a midpoint of the high resistance state and the low resistance state of the memory cell set. | 05-20-2010 |
20100135066 | BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY - A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed. | 06-03-2010 |
20100210095 | POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY - Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell. | 08-19-2010 |
20110002161 | PHASE CHANGE MEMORY CELL WITH SELECTING ELEMENT - A memory cell comprising a phase-change memory cell stacked in series with a resistive switch. The resistive switch has a material switchable between a high resistance state and a low resistance state by the application of a voltage. A plurality of memory cells are used to form a memory array. | 01-06-2011 |
20110006276 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 01-13-2011 |
20110032748 | POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY - A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact. | 02-10-2011 |
20120039111 | POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY - A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact. | 02-16-2012 |
20120074466 | 3D MEMORY ARRAY WITH VERTICAL TRANSISTOR - A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell. | 03-29-2012 |
20120074488 | VERTICAL TRANSISTOR WITH HARDENING IMPLATATION - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 03-29-2012 |
20120080725 | VERTICAL TRANSISTOR MEMORY ARRAY - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array. | 04-05-2012 |
20120149183 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 06-14-2012 |
20120199936 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 08-09-2012 |
20120230094 | BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY - A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed. | 09-13-2012 |
20130302948 | 3D ARRAY WITH VERTICAL TRANSISTOR - A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell. | 11-14-2013 |
20140097400 | VERTICAL TRANSISTOR WITH HARDENING IMPLANTATION - A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 04-10-2014 |
20140334228 | LINEARLY RELATED THRESHOLD VOLTAGE OFFSETS - Threshold voltage offsets for threshold voltages are determined. The threshold voltage offsets may be linearly related by a non-zero slope. The threshold voltages are shifted using their respective threshold voltage offsets. The threshold voltages that are shifted by their respective threshold voltage offsets are used to read data from multi-level memory cells. | 11-13-2014 |
20150058683 | RETENTION BASED DEFECTING IN A HYBRID MEMORY SYSTEM - A first page in a memory unit is programmed with one or more pages of the secondary memory. A first time corresponding to the start of the programming of the first page is recorded. A second time corresponding to the completion of the programming of the one or more pages is recorded. A time difference between the first time and the second time is determined. It is determined if the time difference is greater than a threshold. In response to the time difference being greater than the threshold, a retention based defecting process is for the memory unit is disabled. | 02-26-2015 |