Patent application number | Description | Published |
20090146304 | CARBON NANOTUBE INTEGRATED CIRCUIT DEVICES AND METHODS OF FABRICATION THEREFOR USING PROTECTED CATALYST LAYERS - A method of fabricating an integrated circuit device is provided. The method includes sequentially forming a lower interconnection layer, a catalyst layer, and a buffer layer on a semiconductor substrate, forming an interlayer dielectric layer to cover the buffer layer, forming a contact hole through the interlayer dielectric layer so that a top surface of the buffer layer may be partially exposed, removing a portion of the buffer layer exposed by the contact hole so that a top surface of the catalyst layer may be exposed, and growing carbon nanotubes from a portion of the catalyst layer exposed by the contact hole so that the contact hole may be filled with the carbon nanotubes. | 06-11-2009 |
20090302302 | METAL OXIDE RESISTIVE MEMORY AND METHOD OF FABRICATING THE SAME - Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein. | 12-10-2009 |
20100240221 | Methods of Forming Patterns for Semiconductor Devices - Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern. First spacers covering side walls of the first mask pattern and second spacers covering side walls of the second mask pattern are formed. The first mask pattern is removed, and then the substrate is etched in the first region and the second region by using the first spacers as an etch mask in the first region, and the second mask pattern and the second spacers as an etch mask in the second region. | 09-23-2010 |
20100264544 | Device including contact structure and method of forming the same - A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material. | 10-21-2010 |
20100308388 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor. | 12-09-2010 |
20120211072 | Solar Cell And Method Of Manufacturing Same - Example embodiments of a solar cell including a semiconductor substrate, an N emitter layer formed on a light-absorbing surface of the semiconductor substrate, a p+ region formed on the light-absorbing surface of the semiconductor substrate, a first electrode electrically connected to the p+ region, a second electrode separately formed from the first electrode on the light-absorbing surface of the semiconductor substrate and electrically connected to the N emitter layer, and an auxiliary layer inducing an N+ back surface field (BSF) on the opposite surface to the light-absorbing surface of the semiconductor substrate, and a method of manufacturing the solar cell are provided. | 08-23-2012 |
20120247544 | SOLAR CELL - According to example embodiments, a solar cell includes a plurality of unit portions. Each of the unit portions may have a stacked structure including a plurality of photoelectric members and at least one insulating layer disposed between the photoelectric members. The photoelectric members in different levels may have different energy bandgaps. The photoelectric members in a level may be connected to each other. | 10-04-2012 |
20120266933 | SOLAR CELL - According to example embodiments, a solar cell includes a first unit portion, a second unit portion, and an insulating layer. The first and second unit portions may have different bandgaps, and the insulating layer may be between the first unit portion and the second unit portion. | 10-25-2012 |
20130206202 | SOLAR CELL - According to example embodiments, a solar cell includes a photoelectric member on a passivation member. The photoelectric member is configured to convert incident light into current. The passivation member includes protection material for protecting the-photoelectric member and wavelength conversion material configured to convert light that passes through the photoelectric member into different wavelength. | 08-15-2013 |
20130247975 | SOLAR CELL - A solar cell includes a semiconductor layer including a charge carrier produced therein upon exposure to light, and a passivation layer on a side of the semiconductor layer, the passivation layer configured to apply a stress to the semiconductor layer and change a mobility of the charge carrier into a direction in the semiconductor layer. | 09-26-2013 |
20130247982 | SOLAR CELL - A solar cell may include a PN junction including a semiconductor substrate of a first conductivity and an emitter of a second conductivity, a passivation layer on an exposed surface of the semiconductor substrate, a first electrode connected to the semiconductor substrate, and a second electrode connected to the emitter. The passivation layer may be configured to apply stress to the exposed surface of the substrate such that a mobility of minority charge carriers in the semiconductor substrate is decreased in a first direction perpendicular to a boundary surface of the semiconductor substrate and the passivation layer. | 09-26-2013 |
20140174516 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell includes a crystalline photovoltaic layer, a first impurity region having a first conductivity type and a second impurity region having a second conductivity type in the photovoltaic layer, a third impurity region having the first conductivity type in the first impurity region, a fourth impurity region having the second conductivity type in the second impurity region, a first barrier layer and a second barrier layer contacting the third impurity region and the fourth impurity region, respectively, and a first electrode and a second electrode contacting the first barrier layer and the second barrier layer, respectively. The first impurity region and the second impurity region are spaced apart from each other. The third impurity region and the fourth impurity region have an impurity concentration higher than the first impurity region the second impurity region, respectively. | 06-26-2014 |