Patent application number | Description | Published |
20090001577 | METAL LINE OF SEMICONDUCTOR DEVICE WITH A TRIPLE LAYER DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region and a metal line is formed to fill the metal line forming region of the insulation layer. The diffusion barrier is formed between the metal line and the insulation layer. The diffusion barrier has a structure in which a TaSi | 01-01-2009 |
20090001578 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER WITH AN AMORPHOUS TaBN LAYER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device. | 01-01-2009 |
20090001579 | MULTI-LAYERED METAL LINE HAVING AN IMPROVED DIFFUSION BARRIER OF A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A multi-layered metal line of a semiconductor device and a process of forming the same are described. The multi-layered metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is subsequently formed on the semiconductor substrate including the lower metal line and has an upper metal line forming region that exposes a portion of the lower metal line. A diffusion barrier formed on a surface of the upper metal line forming region of the insulation layer. The diffusion barrier includes a W—B—N ternary layer. An upper metal line is finally formed on the diffusion barrier to fill the upper metal line forming region of the insulation layer. | 01-01-2009 |
20090001580 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device having a diffusion barrier including Cr | 01-01-2009 |
20090017619 | METHOD FOR MANUFACTURING METAL SILICIDE LAYER IN A SEMICONDUCTOR DEVICE - A metal suicide layer is fabricated in a semiconductor device. A first metal layer is deposited on a silicon substrate formed with an S interlayer dielectric having a contact hole through PVD. A second metal layer is deposited on the first metal layer through any one of CVD and ALD. Annealing is performed on the silicon substrate which is formed with the first and second metal layers to form the metal silicide. The portions of the second metal layer and the first metal layer which have not reacted during annealing are removed. | 01-15-2009 |
20090153863 | Method of evaluating sensitivity grade of interior material used in vehicles - A method of evaluating the sensitivity grade of an interior material used in vehicles comprises: evaluating sensitivity properties of an interior material before providing noise factors; evaluating sensitivity properties of the interior material after providing noise factors; averaging each of the sensitivity properties evaluated before the provision of noise factors and after the provision of noise factors to obtain the average value (safety factor) of each of the sensitivity properties; comparing the average value of each of the sensitivity properties with a preset target value of each of the sensitivity properties to compute a target value achievement level of each of the sensitivity properties; and determining the sensitivity grade of the interior material based on the sensitivity property with the lowest target value achievement level. By providing an objective standard to evaluate sensitivity properties of an interior material used in vehicles, the present method(s) eliminates the difficulty in communication between customers and manufactures and quality control regarding the sensitivity grade of interior materials used in vehicles. | 06-18-2009 |
20100059890 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device having a diffusion barrier including Cr | 03-11-2010 |
20100082228 | SYSTEM FOR DISPLAYING A CUMULATIVE FUEL ECONOMIC DRIVING AREA AND METHOD THEREOF - The present invention relates to a system and a method for displaying an accumulative fuel economic driving area of a vehicle. A system according to an embodiment includes a vehicle information unit that collects vehicle information and a controller that calculates a fuel economic driving area by using the vehicle information, and calculates an accumulative fuel economic driving area by accumulating respective lighting times of respective zones of the fuel economic driving area and calculating respective accumulation ratios of the respective zones. The system provides the driver with information for fuel economic driving. | 04-01-2010 |
20100119628 | Anti-aging cosmetic composition - The present invention relates to an anti-aging cosmetic composition, and more particularly, the present invention relates to an anti-aging cosmetic composition containing | 05-13-2010 |
20110233781 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER WITH AN AMORPHOUS TaBN LAYER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device. | 09-29-2011 |
20130099304 | 3-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another. | 04-25-2013 |
20140054671 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode. | 02-27-2014 |
20140054672 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode. | 02-27-2014 |
20140054673 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and metal silicide layers configured to be in contact with the pipe connection gate electrode. The electric resistance of the pipe connection gate electrode may be greatly reduced without deteriorating the characteristics of the memory layers by forming the metal silicide layers coming in contact with the pipe connection gate electrode. | 02-27-2014 |
20140054674 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height. | 02-27-2014 |
20150072491 | 3-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another. | 03-12-2015 |
20150079748 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height. | 03-19-2015 |