Patent application number | Description | Published |
20080209722 | Method for forming via hole having fine hole land - A method for forming a via hole having a fine hole land with which the density of circuit patterns can be increased. The method includes forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer. | 09-04-2008 |
20080216314 | METHOD FOR MANUFACTURING THE BGA PACKAGE BOARD - Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed, an insulating layer formed between the first and second external layers, a first outer via hole to electrically connect the first and second external layers to each other, and a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened. The solder ball pad pattern is thinner than the circuit pattern of the second external layer. | 09-11-2008 |
20080223610 | BGA PACKAGE SUBSTRATE AND METHOD OF FABRICATING SAME - Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same. | 09-18-2008 |
20100261348 | Method for fabricating semiconductor package substrate having different thicknesses between wire bonding pad and ball pad - A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment. | 10-14-2010 |
20110095421 | Flip chip package and method of manufacturing the same - There is provided a flip chip package including an electronic device, a board including a conductive pad disposed inside a mounting region of the board on which the electronic device is mounted, and a connection pad disposed outside the mounting region, a resin layer formed on the board and including a trench formed by removing a part of the resin layer, and a dam member provided on the trench and preventing the leakage of an underfill between the mounting region and the connection pad. Since the dam member, formed on the processed resin layer, can prevent the leakage of the underfill, a package defect rate can be lowered, and connection reliability can be improved. | 04-28-2011 |
20110266671 | SUBSTRATE FOR A SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Disclosed herein are a substrate for a semiconductor package and a manufacturing method thereof. The substrate for the semiconductor package, which has a single-sided substrate structure including circuit patterns having a connection pad formed on only an electronic component mounting surface, can directly connect a connection pad on the top of the substrate to external connection terminals on the bottom of the substrate through a connection via formed of a metal plating layer formed in an inner wall of the via hole and a conductive metal paste filled in the via hole. | 11-03-2011 |
20110286191 | Printed circuit board and semiconductor package with the same - Disclosed herein is a printed circuit board. The printed circuit board includes a base substrate including a first region on which a semiconductor chip is mounted and a second region positioned outside the first region, first insulating patterns covering the base substrate and including trenches formed on the second region, and second insulating patterns protruding from the first insulating patterns on the second region. The trench and the second insulating pattern may be used as a structure defining an underfill forming material in a preset shape during the process of forming an underfill. | 11-24-2011 |
20120043128 | Printed circuit board and method of manufacturing the same - The present invention provides a multilayer printed circuit board and a method for manufacturing the same. The printed circuit board includes: an inner circuit layer which is disposed on a first insulating layer; a via land which is disposed on the first insulating layer to be spaced apart from the inner circuit layer and has a hole; a second insulating layer which is disposed on the first insulating layer including the inner circuit layer and the via land; first and second outer circuit layers which are disposed on outer surfaces of the first and second insulating layers, respectively; and a via which passes through the hole of the via land and the first and second insulating layers and electrically interconnects the first and second outer circuit layers. | 02-23-2012 |
20120168212 | PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a base substrate having a metal pattern for a circuit; and a surface roughness provided on the metal pattern, wherein the surface roughness has a first surface roughness in an anchor structure and a second surface roughness having a black oxide layer in a needle structure formed on the first surface roughness. | 07-05-2012 |
20120244662 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component. | 09-27-2012 |
20140030855 | METHOD OF MANUFACTURING FLIP CHIP PACKAGE - A method of manufacturing a flip chip package includes: providing a board including a conductive pad disposed inside a mounting region of the board on which the electronic device is to be mounted, and a connection pad disposed outside the mounting region; forming a resin layer on the board; forming a trench by removing a part of the resin layer or forming an uneven portion at a portion of a surface of the resin layer; forming, on the trench or uneven portion, a dam member preventing leakage of an underfill between the mounting region and the connection pad; and mounting the electronic device on the mounting region. | 01-30-2014 |