| Patent application number | Description | Published |
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| 20080305636 | METHOD OF FORMING FINE PATTERN EMPLOYING SELF-ALIGNED DOUBLE PATTERNING - There are provided a method of forming a fine pattern employing self-aligned double patterning. The method includes providing a substrate. First mask patterns are formed on the substrate. A reactive layer is formed on the substrate having the first mask patterns. The reactive layer adjacent to the first mask patterns is reacted using a chemical attachment process, thereby forming sacrificial layers along outer walls of the first mask patterns. The reactive layer that is not reacted is removed to expose the sacrificial layers. Second mask patterns are formed between the sacrificial layers adjacent to sidewalls of the first mask patterns facing each other. The sacrificial layers are removed to expose the first and second mask patterns and the substrate exposed between the first and second mask patterns. The substrate is etched using the first and second mask patterns as an etching mask. | 12-11-2008 |
| 20080308875 | MASK ROM DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE MASK ROM DEVICE, AND METHODS OF FABRICATING MASK ROM DEVICE AND SEMICONDUCTOR DEVICE - A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity. | 12-18-2008 |
| 20090312413 | Composition Comprising Tanshinone Compounds Isolated From The Extract Of Salviae Miltiorrhizae Radix For Treating Or Preventing Cognitive Dysfunction And The Use Thereof - A composition comprising tanshinone compounds selected from the group consisting of miltirone, 1,2-didehydromiltirone, tanshinone IIA, tanshinone I and dihydrotanshinone I isolated from | 12-17-2009 |
| 20100197685 | NOVEL BENZOFURAN TYPE DERIVATIVES, A COMPOSITION COMPRISING THE SAME FOR TREATING OR PREVENTING COGNITIVE DYSFUNCTION AND THE USE THEREOF - The present invention relates to the novel benzofuran derivatives, the preparation thereof and the composition comprising the same. The benzofuran derivatives of the present invention showed potent inhibiting activity of beta-amyloid aggregation and cell cytotoxicity resulting in stimulating the proliferation of neuronal cells as well as recovering activity of memory learning injury caused by neuronal cell injury using transformed animal model with beta-amyloid precursor gene, therefore the compounds can be useful in treating or preventing cognitive function disorder. | 08-05-2010 |
| 20100285641 | MASK ROM DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE MASK ROM DEVICE, AND METHODS OF FABRICATING MASK ROM DEVICE AND SEMICONDUCTOR DEVICE - A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity. | 11-11-2010 |
| 20110055623 | SOLID STATE STORAGE SYSTEM WITH IMPROVED DATA MERGING EFFICIENCY AND CONTROL METHOD THEREOF - The presented solid state storage system provides an efficient manner of processing read and write operations in a memory block that has a faulty page of memory within it. The solid state storage system includes a flash memory area and a memory controller. The memory controller stores link information into a buffer, allocates a first temporary physical block to resume operations of the bad block past the first bad page, updates and stores mapping information associated with the remaining portions of the bad block past the first bad page, and merges together those valid pages from among the bad block into a final physical block by merging together all prior successfully operated valid pages from among the bad block with any subsequently successfully operated valid pages which are associated with successful operations subsequently to the failure in the first bad page of the bad block. | 03-03-2011 |
| 20110107016 | SOLID STATE STORAGE SYSTEMS AND METHODS FOR FLEXIBLY CONTROLLING WEAR LEVELING - Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements. | 05-05-2011 |
| 20120245165 | NOVEL BENZOFURAN TYPE DERIVATIVES, A COMPOSITION COMPRISING THE SAME FOR TREATING OR PREVENTING COGNITIVE DYSFUNCTION AND THE USE THEREOF - The present invention relates to the novel benzofuran derivatives, the preparation thereof and the composition comprising the same. The benzofuran derivatives of the present invention showed potent inhibiting activity of beta-amyloid aggregation and cell cytotoxicity resulting in stimulating the proliferation of neuronal cells as well as recovering activity of memory learning injury caused by neuronal cell injury using transformed animal model with beta-amyloid precursor gene, therefore the compounds can be useful in treating or preventing cognitive function disorder. | 09-27-2012 |
| 20120245225 | NOVEL BENZOFURAN TYPE DERIVATIVES, A COMPOSITION COMPRISING THE SAME FOR TREATING OR PREVENTING COGNITIVE DYSFUNCTION AND THE USE THEREOF - The present invention relates to the novel benzofuran derivatives, the preparation thereof and the composition comprising the same. The benzofuran derivatives of the present invention showed potent inhibiting activity of beta-amyloid aggregation and cell cytotoxicity resulting in stimulating the proliferation of neuronal cells as well as recovering activity of memory learning injury caused by neuronal cell injury using transformed animal model with beta-amyloid precursor gene, therefore the compounds can be useful in treating or preventing cognitive function disorder. | 09-27-2012 |
| 20120259006 | NOVEL BENZOFURAN TYPE DERIVATIVES, A COMPOSITION COMPRISING THE SAME FOR TREATING OR PREVENTING COGNITIVE DYSFUNCTION AND THE USE THEREOF - The present invention relates to the novel benzofuran derivatives, the preparation thereof and the composition comprising the same. The benzofuran derivatives of the present invention showed potent inhibiting activity of beta-amyloid aggregation and cell cytotoxicity resulting in stimulating the proliferation of neuronal cells as well as recovering activity of memory learning injury caused by neuronal cell injury using transformed animal model with beta-amyloid precursor gene, therefore the compounds can be useful in treating or preventing cognitive function disorder. | 10-11-2012 |
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| 20090065845 | Embedded semiconductor device and method of manufacturing an embedded semiconductor device - Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance. | 03-12-2009 |
| 20090246938 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating extension hole and a scribe connector in the scribe lane region, the penetrating extension hole penetrating the wafer from the first surface to the second surface and extending along the scribe lane region, wherein the scribe connector connects the first and second chip regions spaced apart from each other by the penetrating extension hole. | 10-01-2009 |
| 20100059888 | Mask ROM and method of fabricating the same - A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes. | 03-11-2010 |
| 20100167487 | MASK ROM DEVICES AND METHODS FOR FORMING THE SAME - A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region. | 07-01-2010 |
| 20100320574 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating extension hole and a scribe connector in the scribe lane region, the penetrating extension hole penetrating the wafer from the first surface to the second surface and extending along the scribe lane region, wherein the scribe connector connects the first and second chip regions spaced apart from each other by the penetrating extension hole. | 12-23-2010 |
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| 20100157159 | Method and apparatus for processing video data of liquid crystal display device - A video processing method and apparatus for a liquid crystal display (LCD) device is disclosed. The video processing method for the LCD device includes detecting noise by comparing data of a previous frame with data of a current frame, if the noise is detected, removing the noise from the current frame data, and outputting the resultant current frame data having no noise together with the previous frame data, and comparing the previous frame data with the resultant current frame data having no noise in a lookup table, selecting overdriving data corresponding to the comparison result, and outputting the selected overdriving data. | 06-24-2010 |
| 20100164852 | LIQUID CRYSTAL DISPLAY DEVICE - Disclosed herein is a liquid crystal display device in which an image can be correctly seen even though a screen is rotated. The liquid crystal display device includes a storage unit for storing a plurality of screen change signals, and a timing controller for dividing image data of one horizontal line externally supplied thereto into k odd sub-image data and k even sub-image data, and sequentially outputting the k odd sub-image data and sequentially outputting the k even sub-image data. | 07-01-2010 |
| 20110141153 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - A liquid crystal display device includes: a liquid crystal panel that displays images using a plurality of pixels each including red, green and blue sub-pixels; a gate driving portion that supplies a gate signal to the liquid crystal panel; a data driving portion that supplies a data signal to the liquid crystal panel; and a timing control portion that compares difference of gray level between image signals corresponding to the red, green and blue sub-pixels with a first threshold value and compares difference of gray level between the image signals corresponding to the red, green and blue sub-pixels of neighboring pixels of the plurality of pixels in order to judge type of the image signals, and drives the data driving portion in different methods according to the type of the image signals. | 06-16-2011 |
| 20120146966 | Driving Circuit for Liquid Crystal Display Device and Method for Driving the Same - A driving circuit for a liquid crystal display device includes a liquid crystal panel comprising a plurality of pixel areas to display an image; a data driver configured to drive data lines of the liquid crystal panel; a gate driver configured to drive gate lines of the liquid crystal panel; and a timing controller configured to generate an internal enable signal in an initial driving where an external power is applied, to control the gate and data drivers, and configured to control the gate and data drivers based on synchronization signals, after controlling the driving of the gate driver to be stopped for one frame period when at least one synchronization signals are input from outside. | 06-14-2012 |
| 20120146967 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - The liquid crystal display device includes a display panel for displaying a picture thereon, first to (n)th upper data drive ICs for supplying pixel voltages to one side of each data line in the display panel, first to (n)th bottom data drive ICs for supplying pixel voltages to the other side of each data line, a first timing controller for generating an upper data control signal and for controlling operation of the upper data drive ICs, and a second timing controller for generating a bottom data control signal and for controlling operation of the bottom data drive ICs wherein at least one of the first and second timing controllers analyzes the picture data applied thereto and controls the polarities of the pixel voltages to be forwarded from the upper data drive ICs and the bottom data drive ICs with reference to the result of the analysis. | 06-14-2012 |
