Patent application number | Description | Published |
20080272087 | METHOD FOR FABRICATING PROBE FOR USE IN SCANNING PROBE MICROSCOPE - A method of fabricating a probe tip for use in a scanning probe microscope, includes the steps of: forming a triangular prism provided with a passivation film by patterning a {111} general silicon wafer, the passivation film being deposited on two sidewalls of the triangular prism; etching the silicon wafer to make the triangular prism into a probe tip of a triangular pyramid shape; and removing the passivation film. | 11-06-2008 |
20100210116 | METHODS OF FORMING VAPOR THIN FILMS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME - A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate. | 08-19-2010 |
20100240207 | METHODS OF MANUFACTURING CHARGE TRAP TYPE MEMORY DEVICES - Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process. | 09-23-2010 |
20110049610 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided are a nonvolatile memory device and a method of forming the same. The nonvolatile memory device includes: a semiconductor substrate including a device isolation layer defining an active region; a tunnel insulating layer on the active region; a charge trapping layer on the tunnel insulating layer; a blocking insulating layer on the charge trapping layer and the device isolation layer; a gate electrode on the blocking insulating layer; and a barrier capping layer formed between the device isolation layer and the blocking insulating layer. | 03-03-2011 |
20110165750 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES - In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns. | 07-07-2011 |
20110281379 | METHODS OF FORMING CONDUCTIVE LAYER PATTERNS USING GAS PHASE CLEANING PROCESS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current. | 11-17-2011 |
20130342232 | PROBE CARD AND MANUFACTURING METHOD - There is provided a probe card in contact with pads formed on a plurality of semiconductor dies on a wafer to test the semiconductor dies. The probe card includes a printed circuit board on which a plurality of pads are formed; a block plate having a plurality of grooves and attached to the printed circuit board; a plurality of sub-probe units equipped with a plurality of probe tips in contact with the pads of the semiconductor dies and detachably coupled to the plurality of grooves; and a plurality of interposer/space transformer units interposed between the sub-probe units and the printed circuit board and configured to electrically connect the probe tips to the pads of the printed circuit board and transform a pitch of the pads formed on the printed circuit to a pitch of the plurality of probe tips. | 12-26-2013 |
20140327062 | ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS - An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode. | 11-06-2014 |