| Patent application number | Description | Published |
|---|
| 20090033530 | METHOD OF CONTROLLING PIPELINE ANALOG-TO-DIGITAL CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER IMPLEMENTING THE SAME - Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC. | 02-05-2009 |
| 20090086072 | DUAL CDS/PxGA CIRCUIT - Provided is a dual sampling/pixel gain amplifier (CDS/PxGA) circuit with a shared amplifier, and more particularly, to a dual CDS/PxGA circuit for adjusting a gain of an amplifier based on capacitance. The dual CDS/PxGA circuit comprises: a first sampler for sampling a reset level and a data level of a first pixel; a second sampler for sampling a reset level and a data level of a second pixel; and an operational amplifier for receiving sampling values from the first and second samplers, calculating output signals of the first and second pixels using the sampling values, and amplifying the calculated output signals. Thus, it is possible to reduce a speed of an operational amplifier by using the dual CDS/PxGA structure, reduce power consumption by sharing the operational amplifier, and obtain a variable gain of a wide range by adjusting capacitance using a capacitor array. | 04-02-2009 |
| 20090091383 | GAIN AMPLIFIER HAVING SWITCHED-CAPACITOR STRUCTURE FOR MINIMIZING SETTLING TIME - Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized. | 04-09-2009 |
| 20090091387 | SWITCHED-CAPACITOR VARIABLE GAIN AMPLIFIER HAVING HIGH VOLTAGE GAIN LINEARITY - Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved. | 04-09-2009 |
| 20090096646 | METHOD OF ALGORITHMIC ANALOG-TO-DIGITAL CONVERSION AND ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER - Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit. | 04-16-2009 |
| 20100052643 | BAND-GAP REFERENCE VOLTAGE GENERATOR - A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about | 03-04-2010 |
| 20100066583 | MULTI-STAGE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TODIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD USING THE SAME - A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC. | 03-18-2010 |
| 20100085229 | ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER - Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution. | 04-08-2010 |
| 20100123611 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-DIGITAL CONVERTER AND METHOD OF DRIVING THE SAME - A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved. | 05-20-2010 |
| 20100156469 | HIGH-SPEED MULTI-STAGE VOLTAGE COMPARATOR - A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC). | 06-24-2010 |
| 20100156692 | MULTI-STAGE DUAL SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTOR AND METHOD OF PERFORMING ANALOG-TO-DIGITAL CONVERSION USING THE SAME - A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier. | 06-24-2010 |
| 20110018605 | OFFSET-VOLTAGE CALIBRATION CIRCUIT - Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage. | 01-27-2011 |
| 20110018629 | REFERENCE VOLTAGE SUPPLY CIRCUIT - A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground. | 01-27-2011 |
| 20110032134 | DIGITAL-TO-ANALOG CONVERTER - A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized. Consequently, it is possible to minimize heat noise and device mismatching. | 02-10-2011 |
| 20110102220 | PIPELINE ANALOG-TO-DIGITAL CONVERTER - Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced. | 05-05-2011 |
| 20110121886 | CLOCK DETECTOR AND BIAS CURRENT CONTROL CIRCUIT - Provided are a clock detector and a bias current control circuit. The clock detector outputs a digital code corresponding to the frequency of an input clock, and the bias current control circuit controls a bias current supplied to an analog circuit according to the digital code output from the clock detector. Accordingly, when the clock detector and the bias current control circuit are used, it is possible to minimize the power consumption of an analog circuit by controlling a bias current supplied to an analog circuit according to a digital code corresponding to the frequency of an input clock. | 05-26-2011 |
