Patent application number | Description | Published |
20130335658 | Pixel Architecture for Electronic Displays - An electronic display for providing a visual or video output for an electronic device. The electronic device includes a transistor layer configured to activate a first pixel row and a second pixel row. For each pixel in the first pixel row and the second pixel row, the transistor layer includes a switch transistor, a pixel electrode, and a common electrode. The electronic device further includes a pixel controller for selectively activating each pixel. The pixel controller includes a first gate line, a first drive line, and a second drive line. During operation, the first gate line provides a charge to the pixel electrode for a first pixel in the first pixel row and for a second pixel in the second pixel row, and the first drive line activates the switch transistor for the first pixel, and the second drive line activates the switch transistor for the second pixel. | 12-19-2013 |
20130337596 | Back Channel Etch Metal-Oxide Thin Film Transistor and Process - A method is provided for fabricating an organic light emitting diode (OLED) display. The method includes forming a thin film transistor (TFT) substrate including a first metal layer and a second metal layer. The method also includes depositing a first passivation layer over the second metal layer, and forming a third metal layer over a channel region and a storage capacitor region. The third metal layer is configured to connect to a first portion of the second metal layer that is configured to connect to the first metal layer in a first through-hole through a gate insulator and the first passivation layer. The method further includes depositing a second passivation layer over the third metal layer, and forming an anode layer over the second passivation layer. The anode is configured to connect to a second portion of the third metal layer that is configured to connect to the second metal layer in a second through-hole of the first passivation layer and the second passivation layer. | 12-19-2013 |
20140042427 | Gate Insulator Loss Free Etch-Stop Oxide Thin Film Transistor - A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode. | 02-13-2014 |
20140061656 | Two Doping Regions in Lightly Doped Drain for Thin Film Transistors and Associated Doping Processes - A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose. | 03-06-2014 |
20140070225 | Hydrogenation and Crystallization of Polycrystalline Silicon - A TFT stack for a liquid crystal display is provided. The TFT stack includes a silicon layer that includes a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region. The heavily doped region is hydrogenated. The TFT stack also includes an insulation layer that includes a first portion formed over the lightly doped region and a second portion disposed over the non-doped region and a gate metal electrode layer formed over the second portion of the non-doped region. The TFT stack also includes a first dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer. The heavily doped region is hydrogenated to reduce the dependence of the capacitance between the gate metal electrode and the conductive layer C | 03-13-2014 |
20140084292 | Connection to First Metal Layer in Thin Film Transistor Process - A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer. | 03-27-2014 |
20140103349 | DIFFERENT LIGHTLY DOPED DRAIN LENGTH CONTROL FOR SELF-ALIGN LIGHT DRAIN DOPING PROCESS - A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack. The TFT stack includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes removing the first photoresist layer, and depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area. The method further includes doping the second portion of the doped semiconductor layer with a third doping dose, the first dose being higher than the second dose and the third dose. | 04-17-2014 |
20140104527 | Process Architecture for Color Filter Array in Active Matrix Liquid Crystal Display - An active matrix liquid crystal display having an array of pixels is provided. The display includes a thin film transistor (TFT) for each pixel. The TFT has a gate electrode, a source electrode overlapping with a first area of the gate electrode, and a drain electrode overlapping with a second area with the gate electrode. The display also includes a color filter layer disposed over the TFT. The color filter layer has a first via hole to expose a portion of the drain electrode. The display further includes a metal layer disposed over the color filter layer and covering the gate electrode. The metal layer is configured to connect to the drain electrode through the first via hole. The display also includes an organic insulator layer disposed over the metal layer. The organic insulator layer has a second via hole to expose a first portion of the metal layer and a third via hole to expose a second portion of the metal layer. | 04-17-2014 |
20140120657 | Back Channel Etching Oxide Thin Film Transistor Process Architecture - A method is provided for fabricating a back channel etching (BCE) oxide thin film transistor (TFT) for a liquid crystal display. The method includes forming a first metal layer having a first portion and a second portion over a substrate, depositing a gate insulator over the first metal layer, and disposing a semiconductor layer over the gate insulator. The method also includes depositing a half-tone photoresist to cover a first portion of the semiconductor layer and the first portion of the first metal layer. The half-tone photoresist has a first portion and a second portion thicker than the first portion. The first portion has a via hole above the second portion of the first metal layer. The second portion of the half-tone photoresist covers the first portion of the first metal layer. The method further includes etching a portion of the gate insulator through the via hole such that the second portion of the first metal layer is exposed, removing the first portion of the half-tone photoresist while remaining the second portion of the half-tone photoresist, and etching to remove a second portion of the semiconductor layer that is not covered by the half-tone photoresist. | 05-01-2014 |
20140138637 | FLEXIBLE DISPLAY - A flexible display having an array of pixels or sub-pixels is provided. The display includes a flexible substrate and an array of thin film transistors (TFTs) corresponding to the array of pixels or sub-pixels on the substrate. The display also includes a first plurality of metal lines coupled to gate electrodes of the TFTs and a second plurality of metal lines coupled to source electrodes and drain electrodes of the TFTs. At least one of the first plurality of metal lines and the second plurality of metal lines comprises a non-stretchable portion in the TFT areas and a stretchable portion outside the TFT areas. | 05-22-2014 |
20140203245 | Active Matrix Organic Light Emitting Diode Display Having Variable Optical Path Length for Microcavity - An organic light emitting diode display includes an array of pixels on a substrate. Each pixel includes three sub-pixels that emits light of different wavelengths from each other. The display includes thin film transistors (TFTs) for the sub-pixels on the substrate. Each TFT is separated from each other by a first pixel defining layer. The display also includes a first pixel electrode connected to the TFT for each sub-pixel, a tuning layer on the first pixel electrode, where the tuning layer has a thickness for each sub-pixel such that each sub-pixel has a optical-path length different from another sub-pixel. The display further includes an organic light emitting layer disposed over the tuning layer, and a second pixel defining layer covering a first end of the tuning layer and a second end of the tuning layer opposing to the first end of the tuning layer, and exposing the light emitting layer. | 07-24-2014 |
20140211120 | Third Metal Layer for Thin Film Transistor witih Reduced Defects in Liquid Crystal Display - A liquid crystal display (LCD) includes an array of pixels over a thin film transistor (TFT) substrate. The TFT substrate includes a TFT that has a first metal layer to form a gate electrode and a second metal layer to form a source electrode and a drain electrode for each pixel. The LCD also includes an organic insulation layer disposed over the TFT substrate, where the organic insulator layer has trenches on a top surface. The LCD further includes a third metal layer disposed over the organic insulation layer in the trenches, the trenches having a trench depth at least equal to the thickness of the third metal layer. The LCD also includes a passivation layer over the third metal layer, and a pixel electrode for each pixel over the passivation layer. The LCD further includes a polymer layer over the pixel electrode, and liquid molecules on the polymer layer. | 07-31-2014 |
20140370655 | Gate Insulator Loss Free Etch-Stop Oxide Thin Film Transistor - A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode. | 12-18-2014 |