Patent application number | Description | Published |
20090044062 | Method of testing a memory module and hub of the memory module - A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data. | 02-12-2009 |
20100202180 | MEMORY MODULE CUTTING OFF DM PAD LEAKAGE CURRENT - A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode. | 08-12-2010 |
20110113296 | Method of testing a memory module and hub of the memory module - Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals. | 05-12-2011 |
20110115509 | Semiconductor Devices Including Design for Test Capabilities and Semiconductor Modules and Test Systems Including Such Devices - A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal. | 05-19-2011 |
20110161576 | MEMORY MODULE AND MEMORY SYSTEM COMPRISING MEMORY MODULE - A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal. | 06-30-2011 |
20110176371 | MEMORY MODULE INCLUDING MEMORY BUFFER AND MEMORY SYSTEM HAVING THE SAME - A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal. | 07-21-2011 |
20120182777 | MEMORY MODULE CUTTING OFF DM PAD LEAKAGE CURRENT - A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode. | 07-19-2012 |
20120239903 | ADDRESS TRANSFORMING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - An address transforming circuit that can change a memory mapping when a system is booted includes a switch control signal generating circuit and an address transforming unit. The switch control signal generating circuit generates alternately enabled switch control signals synchronized with a reset signal. The address transforming unit transforms bits of a first address to generate a second address in response to the switch control signals. Accordingly, a semiconductor memory device including the address transforming circuit has a long lifetime and high reliability. | 09-20-2012 |
20140219044 | MEMORY MODULE AND MEMORY SYSTEM COMPRISING SAME - A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal. | 08-07-2014 |