| Patent application number | Description | Published |
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| 20080303065 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - It is an object of the invention to provide a thin, lightweight, high performance, and low in cost semiconductor device and a display device by reducing an arrangement area required for a power supply wiring and a ground wiring of a functional circuit and decreasing a drop in power supply voltage and a rise in ground voltage. In the functional circuit of the semiconductor device and the display device, a power supply wiring and a ground wiring are formed in a comb-like arrangement, and the tips thereof are electrically connected with a first wiring, a second wiring, and a contact between the first wiring and the second wiring, thereby forming in a grid-like arrangement. The drop in power supply voltage and the rise in ground voltage can be decreased and the arrangement area can be decreased in the grid-like arrangement. | 12-11-2008 |
| 20090004846 | WIRING BOARD, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a wiring board having a small-scale and high-performance functional circuit while realizing a multi-layer wiring with a small number of steps. In addition, the invention provides a semiconductor device in which a display device is integrated with such high-performance functional circuit on the same substrate. According to the invention, first to third wirings, first and second interlayer insulating films and first and second contact holes are formed over a substrate having an insulating surface. The second wiring is wider than the first wiring, or the third wiring is wider than the first wiring or the second wiring. The second contact hole has a larger diameter than the first contact hole. | 01-01-2009 |
| 20090072862 | Semiconductor Device and Display Device - The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision. That is, a reliability of the logic synthesis result is improved, therefore, the logic synthesis and an automatic routing of layout are not required to be repeated, which can shorten the design period. | 03-19-2009 |
| 20100327911 | Semiconductor Device and a Display Device - The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision. That is, a reliability of the logic synthesis result is improved, therefore, the logic synthesis and an automatic routing of layout are not required to be repeated, which can shorten the design period. | 12-30-2010 |
| Patent application number | Description | Published |
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| 20090077319 | Arithmetic Processing Device and Electronic Appliance Using Arithmetic Processing Device - A CPU incorporating a cache memory is provided, in which a high processing speed and low power consumption are realized at the same time. A CPU incorporating an associative cache memory including a plurality of sets is provided, which includes a means for observing a cache memory area which does not contribute to improving processing performance of the CPU in accordance with an operating condition, and changing such a cache memory area to a resting state dynamically. By employing such a structure, a high-performance and low-power consumption CPU can be provided. | 03-19-2009 |
| 20090218576 | THIN-FILM TRANSISTOR AND DISPLAY DEVICE - A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers. | 09-03-2009 |
| 20090236600 | THIN FILM TRANSISTOR AND DISPLAY DEVICE - A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer. | 09-24-2009 |
| 20090269911 | NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate ( | 10-29-2009 |
