Patent application number | Description | Published |
20080263392 | JTAG controlled self-repair after packaging - An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer. | 10-23-2008 |
20100013510 | SYSTEMS AND METHODS FOR DEFECT TESTING OF EXTERNALLY ACCESSIBLE INTEGRATED CIRCUIT INTERCONNECTS - Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad. | 01-21-2010 |
20100097871 | REDUNDANT MEMORY ARRAY FOR REPLACING MEMORY SECTIONS OF MAIN MEMORY - Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array. | 04-22-2010 |
20100205489 | JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING - An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer. | 08-12-2010 |
20110035635 | JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING - An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer. | 02-10-2011 |
20110122715 | REDUNDANT MEMORY ARRAY FOR REPLACING MEMORY SECTIONS OF MAIN MEMORY - Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array. | 05-26-2011 |
20110273185 | METHODS FOR DEFECT TESTING OF EXTERNALLY ACCESSIBLE INTEGRATED CIRCUIT INTERCONNECTS - Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad. | 11-10-2011 |
20120120749 | JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING - An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer. | 05-17-2012 |
20120182817 | REDUNDANT MEMORY ARRAY FOR REPLACING MEMORY SECTIONS OF MAIN MEMORY - Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array. | 07-19-2012 |
20130254513 | REDUNDANT MEMORY ARRAY FOR REPLACING MEMORY SECTIONS OF MAIN MEMORY - Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array. | 09-26-2013 |