Patent application number | Description | Published |
20090072013 | NANO-SCALE PARTICLE PASTE FOR WIRING MICROELECTRONIC DEVICES USING INK-JET PRINTING - Nano-scale particle paste may be used for on-die routing and other applications using deposition and inkjet printing. A metal paste is applied to a surface of a die to electrically couple two spaced apart connection points of the die. Alternatively, or in addition, the paste may contain carbon nanotubes. The paste may be used on other surfaces as well. | 03-19-2009 |
20090109643 | THIN SEMICONDUCTOR DEVICE PACKAGE - A thin semiconductor device package, comprising a thin substrate at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end. | 04-30-2009 |
20090320281 | Apparatus and methods of forming package-on-package interconnects - Embodiments of an apparatus and methods of forming a package on package interconnect and its application to the packaging of microelectronic devices are described herein. Other embodiments may be described and claimed. | 12-31-2009 |
20100258927 | Package-on-package interconnect stiffener - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 10-14-2010 |
20100309704 | In-pakage microelectronic apparatus, and methods of using same - A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s. | 12-09-2010 |
20130292838 | PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 11-07-2013 |
20140167217 | PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER - Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed. | 06-19-2014 |
20150194401 | FORMING SACRIFICIAL COMPOSITE MATERIALS FOR PACKAGE-ON-PACKAGE ARCHITECTURES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed. | 07-09-2015 |